1*7a261bafSVijai Kumar K /* 2*7a261bafSVijai Kumar K * Shakti C-class SoC emulation 3*7a261bafSVijai Kumar K * 4*7a261bafSVijai Kumar K * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com> 5*7a261bafSVijai Kumar K * 6*7a261bafSVijai Kumar K * This program is free software; you can redistribute it and/or modify it 7*7a261bafSVijai Kumar K * under the terms and conditions of the GNU General Public License, 8*7a261bafSVijai Kumar K * version 2 or later, as published by the Free Software Foundation. 9*7a261bafSVijai Kumar K * 10*7a261bafSVijai Kumar K * This program is distributed in the hope it will be useful, but WITHOUT 11*7a261bafSVijai Kumar K * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*7a261bafSVijai Kumar K * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*7a261bafSVijai Kumar K * more details. 14*7a261bafSVijai Kumar K * 15*7a261bafSVijai Kumar K * You should have received a copy of the GNU General Public License along with 16*7a261bafSVijai Kumar K * this program. If not, see <http://www.gnu.org/licenses/>. 17*7a261bafSVijai Kumar K */ 18*7a261bafSVijai Kumar K 19*7a261bafSVijai Kumar K #ifndef HW_SHAKTI_H 20*7a261bafSVijai Kumar K #define HW_SHAKTI_H 21*7a261bafSVijai Kumar K 22*7a261bafSVijai Kumar K #include "hw/riscv/riscv_hart.h" 23*7a261bafSVijai Kumar K #include "hw/boards.h" 24*7a261bafSVijai Kumar K 25*7a261bafSVijai Kumar K #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" 26*7a261bafSVijai Kumar K #define RISCV_SHAKTI_SOC(obj) \ 27*7a261bafSVijai Kumar K OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC) 28*7a261bafSVijai Kumar K 29*7a261bafSVijai Kumar K typedef struct ShaktiCSoCState { 30*7a261bafSVijai Kumar K /*< private >*/ 31*7a261bafSVijai Kumar K DeviceState parent_obj; 32*7a261bafSVijai Kumar K 33*7a261bafSVijai Kumar K /*< public >*/ 34*7a261bafSVijai Kumar K RISCVHartArrayState cpus; 35*7a261bafSVijai Kumar K DeviceState *plic; 36*7a261bafSVijai Kumar K MemoryRegion rom; 37*7a261bafSVijai Kumar K 38*7a261bafSVijai Kumar K } ShaktiCSoCState; 39*7a261bafSVijai Kumar K 40*7a261bafSVijai Kumar K #define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c") 41*7a261bafSVijai Kumar K #define RISCV_SHAKTI_MACHINE(obj) \ 42*7a261bafSVijai Kumar K OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE) 43*7a261bafSVijai Kumar K typedef struct ShaktiCMachineState { 44*7a261bafSVijai Kumar K /*< private >*/ 45*7a261bafSVijai Kumar K MachineState parent_obj; 46*7a261bafSVijai Kumar K 47*7a261bafSVijai Kumar K /*< public >*/ 48*7a261bafSVijai Kumar K ShaktiCSoCState soc; 49*7a261bafSVijai Kumar K } ShaktiCMachineState; 50*7a261bafSVijai Kumar K 51*7a261bafSVijai Kumar K enum { 52*7a261bafSVijai Kumar K SHAKTI_C_ROM, 53*7a261bafSVijai Kumar K SHAKTI_C_RAM, 54*7a261bafSVijai Kumar K SHAKTI_C_UART, 55*7a261bafSVijai Kumar K SHAKTI_C_GPIO, 56*7a261bafSVijai Kumar K SHAKTI_C_PLIC, 57*7a261bafSVijai Kumar K SHAKTI_C_CLINT, 58*7a261bafSVijai Kumar K SHAKTI_C_I2C, 59*7a261bafSVijai Kumar K }; 60*7a261bafSVijai Kumar K 61*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_HART_CONFIG "MS" 62*7a261bafSVijai Kumar K /* Including Interrupt ID 0 (no interrupt)*/ 63*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_NUM_SOURCES 28 64*7a261bafSVijai Kumar K /* Excluding Priority 0 */ 65*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_NUM_PRIORITIES 2 66*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_PRIORITY_BASE 0x04 67*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_PENDING_BASE 0x1000 68*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_ENABLE_BASE 0x2000 69*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80 70*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000 71*7a261bafSVijai Kumar K #define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000 72*7a261bafSVijai Kumar K 73*7a261bafSVijai Kumar K #endif 74