17a261bafSVijai Kumar K /* 27a261bafSVijai Kumar K * Shakti C-class SoC emulation 37a261bafSVijai Kumar K * 47a261bafSVijai Kumar K * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com> 57a261bafSVijai Kumar K * 67a261bafSVijai Kumar K * This program is free software; you can redistribute it and/or modify it 77a261bafSVijai Kumar K * under the terms and conditions of the GNU General Public License, 87a261bafSVijai Kumar K * version 2 or later, as published by the Free Software Foundation. 97a261bafSVijai Kumar K * 107a261bafSVijai Kumar K * This program is distributed in the hope it will be useful, but WITHOUT 117a261bafSVijai Kumar K * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 127a261bafSVijai Kumar K * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 137a261bafSVijai Kumar K * more details. 147a261bafSVijai Kumar K * 157a261bafSVijai Kumar K * You should have received a copy of the GNU General Public License along with 167a261bafSVijai Kumar K * this program. If not, see <http://www.gnu.org/licenses/>. 177a261bafSVijai Kumar K */ 187a261bafSVijai Kumar K 1952581c71SMarkus Armbruster #ifndef HW_SHAKTI_C_H 2052581c71SMarkus Armbruster #define HW_SHAKTI_C_H 217a261bafSVijai Kumar K 227a261bafSVijai Kumar K #include "hw/riscv/riscv_hart.h" 237a261bafSVijai Kumar K #include "hw/boards.h" 248a2aca3dSVijai Kumar K #include "hw/char/shakti_uart.h" 257a261bafSVijai Kumar K 267a261bafSVijai Kumar K #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" 277a261bafSVijai Kumar K #define RISCV_SHAKTI_SOC(obj) \ 287a261bafSVijai Kumar K OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC) 297a261bafSVijai Kumar K 307a261bafSVijai Kumar K typedef struct ShaktiCSoCState { 317a261bafSVijai Kumar K /*< private >*/ 327a261bafSVijai Kumar K DeviceState parent_obj; 337a261bafSVijai Kumar K 347a261bafSVijai Kumar K /*< public >*/ 357a261bafSVijai Kumar K RISCVHartArrayState cpus; 367a261bafSVijai Kumar K DeviceState *plic; 378a2aca3dSVijai Kumar K ShaktiUartState uart; 387a261bafSVijai Kumar K MemoryRegion rom; 397a261bafSVijai Kumar K 407a261bafSVijai Kumar K } ShaktiCSoCState; 417a261bafSVijai Kumar K 427a261bafSVijai Kumar K #define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c") 437a261bafSVijai Kumar K #define RISCV_SHAKTI_MACHINE(obj) \ 447a261bafSVijai Kumar K OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE) 457a261bafSVijai Kumar K typedef struct ShaktiCMachineState { 467a261bafSVijai Kumar K /*< private >*/ 477a261bafSVijai Kumar K MachineState parent_obj; 487a261bafSVijai Kumar K 497a261bafSVijai Kumar K /*< public >*/ 507a261bafSVijai Kumar K ShaktiCSoCState soc; 517a261bafSVijai Kumar K } ShaktiCMachineState; 527a261bafSVijai Kumar K 537a261bafSVijai Kumar K enum { 547a261bafSVijai Kumar K SHAKTI_C_ROM, 557a261bafSVijai Kumar K SHAKTI_C_RAM, 567a261bafSVijai Kumar K SHAKTI_C_UART, 577a261bafSVijai Kumar K SHAKTI_C_GPIO, 587a261bafSVijai Kumar K SHAKTI_C_PLIC, 597a261bafSVijai Kumar K SHAKTI_C_CLINT, 607a261bafSVijai Kumar K SHAKTI_C_I2C, 617a261bafSVijai Kumar K }; 627a261bafSVijai Kumar K 637a261bafSVijai Kumar K #define SHAKTI_C_PLIC_HART_CONFIG "MS" 647a261bafSVijai Kumar K /* Including Interrupt ID 0 (no interrupt)*/ 657a261bafSVijai Kumar K #define SHAKTI_C_PLIC_NUM_SOURCES 28 667a261bafSVijai Kumar K /* Excluding Priority 0 */ 677a261bafSVijai Kumar K #define SHAKTI_C_PLIC_NUM_PRIORITIES 2 68*5decd2c5SBin Meng #define SHAKTI_C_PLIC_PRIORITY_BASE 0x00 697a261bafSVijai Kumar K #define SHAKTI_C_PLIC_PENDING_BASE 0x1000 707a261bafSVijai Kumar K #define SHAKTI_C_PLIC_ENABLE_BASE 0x2000 717a261bafSVijai Kumar K #define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80 727a261bafSVijai Kumar K #define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000 737a261bafSVijai Kumar K #define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000 747a261bafSVijai Kumar K 757a261bafSVijai Kumar K #endif 76