1fe0fe473SAlistair Francis /* 2fe0fe473SAlistair Francis * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3fe0fe473SAlistair Francis * 4fe0fe473SAlistair Francis * Copyright (c) 2020 Western Digital 5fe0fe473SAlistair Francis * 6fe0fe473SAlistair Francis * This program is free software; you can redistribute it and/or modify it 7fe0fe473SAlistair Francis * under the terms and conditions of the GNU General Public License, 8fe0fe473SAlistair Francis * version 2 or later, as published by the Free Software Foundation. 9fe0fe473SAlistair Francis * 10fe0fe473SAlistair Francis * This program is distributed in the hope it will be useful, but WITHOUT 11fe0fe473SAlistair Francis * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12fe0fe473SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13fe0fe473SAlistair Francis * more details. 14fe0fe473SAlistair Francis * 15fe0fe473SAlistair Francis * You should have received a copy of the GNU General Public License along with 16fe0fe473SAlistair Francis * this program. If not, see <http://www.gnu.org/licenses/>. 17fe0fe473SAlistair Francis */ 18fe0fe473SAlistair Francis 19fe0fe473SAlistair Francis #ifndef HW_OPENTITAN_H 20fe0fe473SAlistair Francis #define HW_OPENTITAN_H 21fe0fe473SAlistair Francis 22fe0fe473SAlistair Francis #include "hw/riscv/riscv_hart.h" 23b9fc5135SAlistair Francis #include "hw/intc/ibex_plic.h" 24cc411260SAlistair Francis #include "hw/char/ibex_uart.h" 25db1015e9SEduardo Habkost #include "qom/object.h" 26fe0fe473SAlistair Francis 27fe0fe473SAlistair Francis #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" 288063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC) 29fe0fe473SAlistair Francis 30db1015e9SEduardo Habkost struct LowRISCIbexSoCState { 31fe0fe473SAlistair Francis /*< private >*/ 32fe0fe473SAlistair Francis SysBusDevice parent_obj; 33fe0fe473SAlistair Francis 34fe0fe473SAlistair Francis /*< public >*/ 35fe0fe473SAlistair Francis RISCVHartArrayState cpus; 36b9fc5135SAlistair Francis IbexPlicState plic; 37cc411260SAlistair Francis IbexUartState uart; 38b9fc5135SAlistair Francis 39fe0fe473SAlistair Francis MemoryRegion flash_mem; 40fe0fe473SAlistair Francis MemoryRegion rom; 41db1015e9SEduardo Habkost }; 42fe0fe473SAlistair Francis 43fe0fe473SAlistair Francis typedef struct OpenTitanState { 44fe0fe473SAlistair Francis /*< private >*/ 45fe0fe473SAlistair Francis SysBusDevice parent_obj; 46fe0fe473SAlistair Francis 47fe0fe473SAlistair Francis /*< public >*/ 48fe0fe473SAlistair Francis LowRISCIbexSoCState soc; 49fe0fe473SAlistair Francis } OpenTitanState; 50fe0fe473SAlistair Francis 51fe0fe473SAlistair Francis enum { 5230c717cbSEduardo Habkost IBEX_DEV_ROM, 5330c717cbSEduardo Habkost IBEX_DEV_RAM, 5430c717cbSEduardo Habkost IBEX_DEV_FLASH, 5530c717cbSEduardo Habkost IBEX_DEV_UART, 5630c717cbSEduardo Habkost IBEX_DEV_GPIO, 5730c717cbSEduardo Habkost IBEX_DEV_SPI, 58*d31e970aSAlistair Francis IBEX_DEV_I2C, 59*d31e970aSAlistair Francis IBEX_DEV_PATTGEN, 6030c717cbSEduardo Habkost IBEX_DEV_RV_TIMER, 61*d31e970aSAlistair Francis IBEX_DEV_SENSOR_CTRL, 62*d31e970aSAlistair Francis IBEX_DEV_OTP_CTRL, 6330c717cbSEduardo Habkost IBEX_DEV_PWRMGR, 6430c717cbSEduardo Habkost IBEX_DEV_RSTMGR, 6530c717cbSEduardo Habkost IBEX_DEV_CLKMGR, 6630c717cbSEduardo Habkost IBEX_DEV_PINMUX, 67*d31e970aSAlistair Francis IBEX_DEV_PADCTRL, 68*d31e970aSAlistair Francis IBEX_DEV_USBDEV, 69*d31e970aSAlistair Francis IBEX_DEV_FLASH_CTRL, 70*d31e970aSAlistair Francis IBEX_DEV_PLIC, 71*d31e970aSAlistair Francis IBEX_DEV_AES, 72*d31e970aSAlistair Francis IBEX_DEV_HMAC, 73*d31e970aSAlistair Francis IBEX_DEV_KMAC, 74*d31e970aSAlistair Francis IBEX_DEV_KEYMGR, 75*d31e970aSAlistair Francis IBEX_DEV_CSRNG, 76*d31e970aSAlistair Francis IBEX_DEV_ENTROPY, 77*d31e970aSAlistair Francis IBEX_DEV_EDNO, 78*d31e970aSAlistair Francis IBEX_DEV_EDN1, 7930c717cbSEduardo Habkost IBEX_DEV_ALERT_HANDLER, 8030c717cbSEduardo Habkost IBEX_DEV_NMI_GEN, 81*d31e970aSAlistair Francis IBEX_DEV_OTBN, 82fe0fe473SAlistair Francis }; 83fe0fe473SAlistair Francis 84cc411260SAlistair Francis enum { 85cc411260SAlistair Francis IBEX_UART_RX_PARITY_ERR_IRQ = 0x28, 86cc411260SAlistair Francis IBEX_UART_RX_TIMEOUT_IRQ = 0x27, 87cc411260SAlistair Francis IBEX_UART_RX_BREAK_ERR_IRQ = 0x26, 88cc411260SAlistair Francis IBEX_UART_RX_FRAME_ERR_IRQ = 0x25, 89cc411260SAlistair Francis IBEX_UART_RX_OVERFLOW_IRQ = 0x24, 90cc411260SAlistair Francis IBEX_UART_TX_EMPTY_IRQ = 0x23, 91cc411260SAlistair Francis IBEX_UART_RX_WATERMARK_IRQ = 0x22, 92cc411260SAlistair Francis IBEX_UART_TX_WATERMARK_IRQ = 0x21, 93cc411260SAlistair Francis }; 94cc411260SAlistair Francis 95fe0fe473SAlistair Francis #endif 96