1fe0fe473SAlistair Francis /* 2fe0fe473SAlistair Francis * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3fe0fe473SAlistair Francis * 4fe0fe473SAlistair Francis * Copyright (c) 2020 Western Digital 5fe0fe473SAlistair Francis * 6fe0fe473SAlistair Francis * This program is free software; you can redistribute it and/or modify it 7fe0fe473SAlistair Francis * under the terms and conditions of the GNU General Public License, 8fe0fe473SAlistair Francis * version 2 or later, as published by the Free Software Foundation. 9fe0fe473SAlistair Francis * 10fe0fe473SAlistair Francis * This program is distributed in the hope it will be useful, but WITHOUT 11fe0fe473SAlistair Francis * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12fe0fe473SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13fe0fe473SAlistair Francis * more details. 14fe0fe473SAlistair Francis * 15fe0fe473SAlistair Francis * You should have received a copy of the GNU General Public License along with 16fe0fe473SAlistair Francis * this program. If not, see <http://www.gnu.org/licenses/>. 17fe0fe473SAlistair Francis */ 18fe0fe473SAlistair Francis 19fe0fe473SAlistair Francis #ifndef HW_OPENTITAN_H 20fe0fe473SAlistair Francis #define HW_OPENTITAN_H 21fe0fe473SAlistair Francis 22fe0fe473SAlistair Francis #include "hw/riscv/riscv_hart.h" 23ef631006SAlistair Francis #include "hw/intc/sifive_plic.h" 24cc411260SAlistair Francis #include "hw/char/ibex_uart.h" 253ef64344SAlistair Francis #include "hw/timer/ibex_timer.h" 269972479fSWilfred Mallawa #include "hw/ssi/ibex_spi_host.h" 27db1015e9SEduardo Habkost #include "qom/object.h" 28fe0fe473SAlistair Francis 29fe0fe473SAlistair Francis #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" 308063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC) 31fe0fe473SAlistair Francis 329972479fSWilfred Mallawa enum { 339972479fSWilfred Mallawa OPENTITAN_SPI_HOST0, 349972479fSWilfred Mallawa OPENTITAN_SPI_HOST1, 359972479fSWilfred Mallawa OPENTITAN_NUM_SPI_HOSTS, 369972479fSWilfred Mallawa }; 379972479fSWilfred Mallawa 38db1015e9SEduardo Habkost struct LowRISCIbexSoCState { 39fe0fe473SAlistair Francis /*< private >*/ 40fe0fe473SAlistair Francis SysBusDevice parent_obj; 41fe0fe473SAlistair Francis 42fe0fe473SAlistair Francis /*< public >*/ 43fe0fe473SAlistair Francis RISCVHartArrayState cpus; 44ef631006SAlistair Francis SiFivePLICState plic; 45cc411260SAlistair Francis IbexUartState uart; 463ef64344SAlistair Francis IbexTimerState timer; 479972479fSWilfred Mallawa IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS]; 48b9fc5135SAlistair Francis 49a06fded8SAlistair Francis uint32_t resetvec; 50a06fded8SAlistair Francis 51fe0fe473SAlistair Francis MemoryRegion flash_mem; 52fe0fe473SAlistair Francis MemoryRegion rom; 53bb7e0cdeSAlistair Francis MemoryRegion flash_alias; 54db1015e9SEduardo Habkost }; 55fe0fe473SAlistair Francis 56fe0fe473SAlistair Francis typedef struct OpenTitanState { 57fe0fe473SAlistair Francis /*< private >*/ 58fe0fe473SAlistair Francis SysBusDevice parent_obj; 59fe0fe473SAlistair Francis 60fe0fe473SAlistair Francis /*< public >*/ 61fe0fe473SAlistair Francis LowRISCIbexSoCState soc; 62fe0fe473SAlistair Francis } OpenTitanState; 63fe0fe473SAlistair Francis 64fe0fe473SAlistair Francis enum { 6530c717cbSEduardo Habkost IBEX_DEV_ROM, 6630c717cbSEduardo Habkost IBEX_DEV_RAM, 6730c717cbSEduardo Habkost IBEX_DEV_FLASH, 68bb7e0cdeSAlistair Francis IBEX_DEV_FLASH_VIRTUAL, 6930c717cbSEduardo Habkost IBEX_DEV_UART, 70aecabd50SWilfred Mallawa IBEX_DEV_SPI_DEVICE, 71aecabd50SWilfred Mallawa IBEX_DEV_SPI_HOST0, 72aecabd50SWilfred Mallawa IBEX_DEV_SPI_HOST1, 7330c717cbSEduardo Habkost IBEX_DEV_GPIO, 74d31e970aSAlistair Francis IBEX_DEV_I2C, 75d31e970aSAlistair Francis IBEX_DEV_PATTGEN, 763ef64344SAlistair Francis IBEX_DEV_TIMER, 77d31e970aSAlistair Francis IBEX_DEV_SENSOR_CTRL, 78d31e970aSAlistair Francis IBEX_DEV_OTP_CTRL, 79bf8803c6SWilfred Mallawa IBEX_DEV_LC_CTRL, 8030c717cbSEduardo Habkost IBEX_DEV_PWRMGR, 8130c717cbSEduardo Habkost IBEX_DEV_RSTMGR, 8230c717cbSEduardo Habkost IBEX_DEV_CLKMGR, 8330c717cbSEduardo Habkost IBEX_DEV_PINMUX, 84aefd1108SWilfred Mallawa IBEX_DEV_AON_TIMER, 85d31e970aSAlistair Francis IBEX_DEV_USBDEV, 86d31e970aSAlistair Francis IBEX_DEV_FLASH_CTRL, 87d31e970aSAlistair Francis IBEX_DEV_PLIC, 88d31e970aSAlistair Francis IBEX_DEV_AES, 89d31e970aSAlistair Francis IBEX_DEV_HMAC, 90d31e970aSAlistair Francis IBEX_DEV_KMAC, 91d31e970aSAlistair Francis IBEX_DEV_KEYMGR, 92d31e970aSAlistair Francis IBEX_DEV_CSRNG, 93d31e970aSAlistair Francis IBEX_DEV_ENTROPY, 94d31e970aSAlistair Francis IBEX_DEV_EDNO, 95d31e970aSAlistair Francis IBEX_DEV_EDN1, 9630c717cbSEduardo Habkost IBEX_DEV_ALERT_HANDLER, 97*7ae71462SWilfred Mallawa IBEX_DEV_SRAM_CTRL, 98d31e970aSAlistair Francis IBEX_DEV_OTBN, 99*7ae71462SWilfred Mallawa IBEX_DEV_IBEX_CFG, 100fe0fe473SAlistair Francis }; 101fe0fe473SAlistair Francis 102cc411260SAlistair Francis enum { 103d4cad544SAlistair Francis IBEX_UART0_TX_WATERMARK_IRQ = 1, 1049972479fSWilfred Mallawa IBEX_UART0_RX_WATERMARK_IRQ = 2, 1059972479fSWilfred Mallawa IBEX_UART0_TX_EMPTY_IRQ = 3, 1069972479fSWilfred Mallawa IBEX_UART0_RX_OVERFLOW_IRQ = 4, 1079972479fSWilfred Mallawa IBEX_UART0_RX_FRAME_ERR_IRQ = 5, 1089972479fSWilfred Mallawa IBEX_UART0_RX_BREAK_ERR_IRQ = 6, 1099972479fSWilfred Mallawa IBEX_UART0_RX_TIMEOUT_IRQ = 7, 1109972479fSWilfred Mallawa IBEX_UART0_RX_PARITY_ERR_IRQ = 8, 111*7ae71462SWilfred Mallawa IBEX_TIMER_TIMEREXPIRED0_0 = 124, 112*7ae71462SWilfred Mallawa IBEX_SPI_HOST0_ERR_IRQ = 131, 113*7ae71462SWilfred Mallawa IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132, 114*7ae71462SWilfred Mallawa IBEX_SPI_HOST1_ERR_IRQ = 133, 115*7ae71462SWilfred Mallawa IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134, 116cc411260SAlistair Francis }; 117cc411260SAlistair Francis 118fe0fe473SAlistair Francis #endif 119