xref: /qemu/include/hw/riscv/opentitan.h (revision 3ef6434409c575e11faf537ce50ca05426c78940)
1fe0fe473SAlistair Francis /*
2fe0fe473SAlistair Francis  * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3fe0fe473SAlistair Francis  *
4fe0fe473SAlistair Francis  * Copyright (c) 2020 Western Digital
5fe0fe473SAlistair Francis  *
6fe0fe473SAlistair Francis  * This program is free software; you can redistribute it and/or modify it
7fe0fe473SAlistair Francis  * under the terms and conditions of the GNU General Public License,
8fe0fe473SAlistair Francis  * version 2 or later, as published by the Free Software Foundation.
9fe0fe473SAlistair Francis  *
10fe0fe473SAlistair Francis  * This program is distributed in the hope it will be useful, but WITHOUT
11fe0fe473SAlistair Francis  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12fe0fe473SAlistair Francis  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13fe0fe473SAlistair Francis  * more details.
14fe0fe473SAlistair Francis  *
15fe0fe473SAlistair Francis  * You should have received a copy of the GNU General Public License along with
16fe0fe473SAlistair Francis  * this program.  If not, see <http://www.gnu.org/licenses/>.
17fe0fe473SAlistair Francis  */
18fe0fe473SAlistair Francis 
19fe0fe473SAlistair Francis #ifndef HW_OPENTITAN_H
20fe0fe473SAlistair Francis #define HW_OPENTITAN_H
21fe0fe473SAlistair Francis 
22fe0fe473SAlistair Francis #include "hw/riscv/riscv_hart.h"
23b9fc5135SAlistair Francis #include "hw/intc/ibex_plic.h"
24cc411260SAlistair Francis #include "hw/char/ibex_uart.h"
25*3ef64344SAlistair Francis #include "hw/timer/ibex_timer.h"
26db1015e9SEduardo Habkost #include "qom/object.h"
27fe0fe473SAlistair Francis 
28fe0fe473SAlistair Francis #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
298063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
30fe0fe473SAlistair Francis 
31db1015e9SEduardo Habkost struct LowRISCIbexSoCState {
32fe0fe473SAlistair Francis     /*< private >*/
33fe0fe473SAlistair Francis     SysBusDevice parent_obj;
34fe0fe473SAlistair Francis 
35fe0fe473SAlistair Francis     /*< public >*/
36fe0fe473SAlistair Francis     RISCVHartArrayState cpus;
37b9fc5135SAlistair Francis     IbexPlicState plic;
38cc411260SAlistair Francis     IbexUartState uart;
39*3ef64344SAlistair Francis     IbexTimerState timer;
40b9fc5135SAlistair Francis 
41fe0fe473SAlistair Francis     MemoryRegion flash_mem;
42fe0fe473SAlistair Francis     MemoryRegion rom;
43db1015e9SEduardo Habkost };
44fe0fe473SAlistair Francis 
45fe0fe473SAlistair Francis typedef struct OpenTitanState {
46fe0fe473SAlistair Francis     /*< private >*/
47fe0fe473SAlistair Francis     SysBusDevice parent_obj;
48fe0fe473SAlistair Francis 
49fe0fe473SAlistair Francis     /*< public >*/
50fe0fe473SAlistair Francis     LowRISCIbexSoCState soc;
51fe0fe473SAlistair Francis } OpenTitanState;
52fe0fe473SAlistair Francis 
53fe0fe473SAlistair Francis enum {
5430c717cbSEduardo Habkost     IBEX_DEV_ROM,
5530c717cbSEduardo Habkost     IBEX_DEV_RAM,
5630c717cbSEduardo Habkost     IBEX_DEV_FLASH,
5730c717cbSEduardo Habkost     IBEX_DEV_UART,
5830c717cbSEduardo Habkost     IBEX_DEV_GPIO,
5930c717cbSEduardo Habkost     IBEX_DEV_SPI,
60d31e970aSAlistair Francis     IBEX_DEV_I2C,
61d31e970aSAlistair Francis     IBEX_DEV_PATTGEN,
62*3ef64344SAlistair Francis     IBEX_DEV_TIMER,
63d31e970aSAlistair Francis     IBEX_DEV_SENSOR_CTRL,
64d31e970aSAlistair Francis     IBEX_DEV_OTP_CTRL,
6530c717cbSEduardo Habkost     IBEX_DEV_PWRMGR,
6630c717cbSEduardo Habkost     IBEX_DEV_RSTMGR,
6730c717cbSEduardo Habkost     IBEX_DEV_CLKMGR,
6830c717cbSEduardo Habkost     IBEX_DEV_PINMUX,
69d31e970aSAlistair Francis     IBEX_DEV_PADCTRL,
70d31e970aSAlistair Francis     IBEX_DEV_USBDEV,
71d31e970aSAlistair Francis     IBEX_DEV_FLASH_CTRL,
72d31e970aSAlistair Francis     IBEX_DEV_PLIC,
73d31e970aSAlistair Francis     IBEX_DEV_AES,
74d31e970aSAlistair Francis     IBEX_DEV_HMAC,
75d31e970aSAlistair Francis     IBEX_DEV_KMAC,
76d31e970aSAlistair Francis     IBEX_DEV_KEYMGR,
77d31e970aSAlistair Francis     IBEX_DEV_CSRNG,
78d31e970aSAlistair Francis     IBEX_DEV_ENTROPY,
79d31e970aSAlistair Francis     IBEX_DEV_EDNO,
80d31e970aSAlistair Francis     IBEX_DEV_EDN1,
8130c717cbSEduardo Habkost     IBEX_DEV_ALERT_HANDLER,
8230c717cbSEduardo Habkost     IBEX_DEV_NMI_GEN,
83d31e970aSAlistair Francis     IBEX_DEV_OTBN,
84fe0fe473SAlistair Francis };
85fe0fe473SAlistair Francis 
86cc411260SAlistair Francis enum {
87*3ef64344SAlistair Francis     IBEX_TIMER_TIMEREXPIRED0_0 = 125,
88d4cad544SAlistair Francis     IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
89d4cad544SAlistair Francis     IBEX_UART0_RX_TIMEOUT_IRQ = 7,
90d4cad544SAlistair Francis     IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
91d4cad544SAlistair Francis     IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
92d4cad544SAlistair Francis     IBEX_UART0_RX_OVERFLOW_IRQ = 4,
93d4cad544SAlistair Francis     IBEX_UART0_TX_EMPTY_IRQ = 3,
94d4cad544SAlistair Francis     IBEX_UART0_RX_WATERMARK_IRQ = 2,
95d4cad544SAlistair Francis     IBEX_UART0_TX_WATERMARK_IRQ = 1,
96cc411260SAlistair Francis };
97cc411260SAlistair Francis 
98fe0fe473SAlistair Francis #endif
99