xref: /qemu/include/hw/riscv/opentitan.h (revision 30c717cb50a6a2b65ffbdb7c95672feb09b26bba)
1fe0fe473SAlistair Francis /*
2fe0fe473SAlistair Francis  * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3fe0fe473SAlistair Francis  *
4fe0fe473SAlistair Francis  * Copyright (c) 2020 Western Digital
5fe0fe473SAlistair Francis  *
6fe0fe473SAlistair Francis  * This program is free software; you can redistribute it and/or modify it
7fe0fe473SAlistair Francis  * under the terms and conditions of the GNU General Public License,
8fe0fe473SAlistair Francis  * version 2 or later, as published by the Free Software Foundation.
9fe0fe473SAlistair Francis  *
10fe0fe473SAlistair Francis  * This program is distributed in the hope it will be useful, but WITHOUT
11fe0fe473SAlistair Francis  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12fe0fe473SAlistair Francis  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13fe0fe473SAlistair Francis  * more details.
14fe0fe473SAlistair Francis  *
15fe0fe473SAlistair Francis  * You should have received a copy of the GNU General Public License along with
16fe0fe473SAlistair Francis  * this program.  If not, see <http://www.gnu.org/licenses/>.
17fe0fe473SAlistair Francis  */
18fe0fe473SAlistair Francis 
19fe0fe473SAlistair Francis #ifndef HW_OPENTITAN_H
20fe0fe473SAlistair Francis #define HW_OPENTITAN_H
21fe0fe473SAlistair Francis 
22fe0fe473SAlistair Francis #include "hw/riscv/riscv_hart.h"
23b9fc5135SAlistair Francis #include "hw/intc/ibex_plic.h"
24cc411260SAlistair Francis #include "hw/char/ibex_uart.h"
25fe0fe473SAlistair Francis 
26fe0fe473SAlistair Francis #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
27fe0fe473SAlistair Francis #define RISCV_IBEX_SOC(obj) \
28fe0fe473SAlistair Francis     OBJECT_CHECK(LowRISCIbexSoCState, (obj), TYPE_RISCV_IBEX_SOC)
29fe0fe473SAlistair Francis 
30fe0fe473SAlistair Francis typedef struct LowRISCIbexSoCState {
31fe0fe473SAlistair Francis     /*< private >*/
32fe0fe473SAlistair Francis     SysBusDevice parent_obj;
33fe0fe473SAlistair Francis 
34fe0fe473SAlistair Francis     /*< public >*/
35fe0fe473SAlistair Francis     RISCVHartArrayState cpus;
36b9fc5135SAlistair Francis     IbexPlicState plic;
37cc411260SAlistair Francis     IbexUartState uart;
38b9fc5135SAlistair Francis 
39fe0fe473SAlistair Francis     MemoryRegion flash_mem;
40fe0fe473SAlistair Francis     MemoryRegion rom;
41fe0fe473SAlistair Francis } LowRISCIbexSoCState;
42fe0fe473SAlistair Francis 
43fe0fe473SAlistair Francis typedef struct OpenTitanState {
44fe0fe473SAlistair Francis     /*< private >*/
45fe0fe473SAlistair Francis     SysBusDevice parent_obj;
46fe0fe473SAlistair Francis 
47fe0fe473SAlistair Francis     /*< public >*/
48fe0fe473SAlistair Francis     LowRISCIbexSoCState soc;
49fe0fe473SAlistair Francis } OpenTitanState;
50fe0fe473SAlistair Francis 
51fe0fe473SAlistair Francis enum {
52*30c717cbSEduardo Habkost     IBEX_DEV_ROM,
53*30c717cbSEduardo Habkost     IBEX_DEV_RAM,
54*30c717cbSEduardo Habkost     IBEX_DEV_FLASH,
55*30c717cbSEduardo Habkost     IBEX_DEV_UART,
56*30c717cbSEduardo Habkost     IBEX_DEV_GPIO,
57*30c717cbSEduardo Habkost     IBEX_DEV_SPI,
58*30c717cbSEduardo Habkost     IBEX_DEV_FLASH_CTRL,
59*30c717cbSEduardo Habkost     IBEX_DEV_RV_TIMER,
60*30c717cbSEduardo Habkost     IBEX_DEV_AES,
61*30c717cbSEduardo Habkost     IBEX_DEV_HMAC,
62*30c717cbSEduardo Habkost     IBEX_DEV_PLIC,
63*30c717cbSEduardo Habkost     IBEX_DEV_PWRMGR,
64*30c717cbSEduardo Habkost     IBEX_DEV_RSTMGR,
65*30c717cbSEduardo Habkost     IBEX_DEV_CLKMGR,
66*30c717cbSEduardo Habkost     IBEX_DEV_PINMUX,
67*30c717cbSEduardo Habkost     IBEX_DEV_ALERT_HANDLER,
68*30c717cbSEduardo Habkost     IBEX_DEV_NMI_GEN,
69*30c717cbSEduardo Habkost     IBEX_DEV_USBDEV,
70*30c717cbSEduardo Habkost     IBEX_DEV_PADCTRL,
71fe0fe473SAlistair Francis };
72fe0fe473SAlistair Francis 
73cc411260SAlistair Francis enum {
74cc411260SAlistair Francis     IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
75cc411260SAlistair Francis     IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
76cc411260SAlistair Francis     IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
77cc411260SAlistair Francis     IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
78cc411260SAlistair Francis     IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
79cc411260SAlistair Francis     IBEX_UART_TX_EMPTY_IRQ = 0x23,
80cc411260SAlistair Francis     IBEX_UART_RX_WATERMARK_IRQ = 0x22,
81cc411260SAlistair Francis     IBEX_UART_TX_WATERMARK_IRQ = 0x21,
82cc411260SAlistair Francis };
83cc411260SAlistair Francis 
84fe0fe473SAlistair Francis #endif
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