1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 * 9 */ 10 11 #ifndef PPC_XIVE2_H 12 #define PPC_XIVE2_H 13 14 #include "hw/ppc/xive2_regs.h" 15 16 /* 17 * XIVE2 Router (POWER10) 18 */ 19 typedef struct Xive2Router { 20 SysBusDevice parent; 21 22 XiveFabric *xfb; 23 } Xive2Router; 24 25 #define TYPE_XIVE2_ROUTER "xive2-router" 26 OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER); 27 28 /* 29 * Configuration flags 30 */ 31 32 #define XIVE2_GEN1_TIMA_OS 0x00000001 33 #define XIVE2_VP_SAVE_RESTORE 0x00000002 34 35 typedef struct Xive2RouterClass { 36 SysBusDeviceClass parent; 37 38 /* XIVE table accessors */ 39 int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 40 Xive2Eas *eas); 41 int (*get_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 42 uint8_t *pq); 43 int (*set_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 44 uint8_t *pq); 45 int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 46 Xive2End *end); 47 int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 48 Xive2End *end, uint8_t word_number); 49 int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 50 Xive2Nvp *nvp); 51 int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 52 Xive2Nvp *nvp, uint8_t word_number); 53 uint8_t (*get_block_id)(Xive2Router *xrtr); 54 uint32_t (*get_config)(Xive2Router *xrtr); 55 } Xive2RouterClass; 56 57 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 58 Xive2Eas *eas); 59 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 60 Xive2End *end); 61 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 62 Xive2End *end, uint8_t word_number); 63 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 64 Xive2Nvp *nvp); 65 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 66 Xive2Nvp *nvp, uint8_t word_number); 67 uint32_t xive2_router_get_config(Xive2Router *xrtr); 68 69 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked); 70 71 /* 72 * XIVE2 Presenter (POWER10) 73 */ 74 75 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 76 uint8_t format, 77 uint8_t nvt_blk, uint32_t nvt_idx, 78 bool cam_ignore, uint32_t logic_serv); 79 80 /* 81 * XIVE2 END ESBs (POWER10) 82 */ 83 84 #define TYPE_XIVE2_END_SOURCE "xive2-end-source" 85 OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE) 86 87 typedef struct Xive2EndSource { 88 DeviceState parent; 89 90 uint32_t nr_ends; 91 92 /* ESB memory region */ 93 uint32_t esb_shift; 94 MemoryRegion esb_mmio; 95 96 Xive2Router *xrtr; 97 } Xive2EndSource; 98 99 /* 100 * XIVE2 Thread Interrupt Management Area (POWER10) 101 */ 102 103 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 104 uint64_t value, unsigned size); 105 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 106 hwaddr offset, unsigned size); 107 108 #endif /* PPC_XIVE2_H */ 109