1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef PPC_XIVE2_H 10 #define PPC_XIVE2_H 11 12 #include "hw/ppc/xive.h" 13 #include "hw/ppc/xive2_regs.h" 14 #include "hw/sysbus.h" 15 16 /* 17 * XIVE2 Router (POWER10) 18 */ 19 typedef struct Xive2Router { 20 SysBusDevice parent; 21 22 XiveFabric *xfb; 23 } Xive2Router; 24 25 #define TYPE_XIVE2_ROUTER "xive2-router" 26 OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER); 27 28 /* 29 * Configuration flags 30 */ 31 32 #define XIVE2_GEN1_TIMA_OS 0x00000001 33 #define XIVE2_VP_SAVE_RESTORE 0x00000002 34 #define XIVE2_THREADID_8BITS 0x00000004 35 36 typedef struct Xive2RouterClass { 37 SysBusDeviceClass parent; 38 39 /* XIVE table accessors */ 40 int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 41 Xive2Eas *eas); 42 int (*get_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 43 uint8_t *pq); 44 int (*set_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 45 uint8_t *pq); 46 int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 47 Xive2End *end); 48 int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 49 Xive2End *end, uint8_t word_number); 50 int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 51 Xive2Nvp *nvp); 52 int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 53 Xive2Nvp *nvp, uint8_t word_number); 54 int (*get_nvgc)(Xive2Router *xrtr, bool crowd, 55 uint8_t nvgc_blk, uint32_t nvgc_idx, 56 Xive2Nvgc *nvgc); 57 int (*write_nvgc)(Xive2Router *xrtr, bool crowd, 58 uint8_t nvgc_blk, uint32_t nvgc_idx, 59 Xive2Nvgc *nvgc); 60 uint8_t (*get_block_id)(Xive2Router *xrtr); 61 uint32_t (*get_config)(Xive2Router *xrtr); 62 } Xive2RouterClass; 63 64 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 65 Xive2Eas *eas); 66 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 67 Xive2End *end); 68 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 69 Xive2End *end, uint8_t word_number); 70 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 71 Xive2Nvp *nvp); 72 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 73 Xive2Nvp *nvp, uint8_t word_number); 74 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, 75 uint8_t nvgc_blk, uint32_t nvgc_idx, 76 Xive2Nvgc *nvgc); 77 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, 78 uint8_t nvgc_blk, uint32_t nvgc_idx, 79 Xive2Nvgc *nvgc); 80 uint32_t xive2_router_get_config(Xive2Router *xrtr); 81 82 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked); 83 84 /* 85 * XIVE2 Presenter (POWER10) 86 */ 87 88 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 89 uint8_t format, 90 uint8_t nvt_blk, uint32_t nvt_idx, 91 bool cam_ignore, uint32_t logic_serv); 92 93 /* 94 * XIVE2 END ESBs (POWER10) 95 */ 96 97 #define TYPE_XIVE2_END_SOURCE "xive2-end-source" 98 OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE) 99 100 typedef struct Xive2EndSource { 101 DeviceState parent; 102 103 uint32_t nr_ends; 104 105 /* ESB memory region */ 106 uint32_t esb_shift; 107 MemoryRegion esb_mmio; 108 109 Xive2Router *xrtr; 110 } Xive2EndSource; 111 112 /* 113 * XIVE2 Thread Interrupt Management Area (POWER10) 114 */ 115 116 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 117 hwaddr offset, uint64_t value, unsigned size); 118 void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 119 hwaddr offset, uint64_t value, unsigned size); 120 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 121 uint64_t value, unsigned size); 122 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 123 hwaddr offset, unsigned size); 124 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 125 hwaddr offset, uint64_t value, unsigned size); 126 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority); 127 void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority); 128 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, 129 hwaddr offset, uint64_t value, unsigned size); 130 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 131 hwaddr offset, uint64_t value, unsigned size); 132 133 #endif /* PPC_XIVE2_H */ 134