xref: /qemu/include/hw/ppc/xive2.h (revision 09a67f3d0e2cb9e66b2ba438de09789527ccb9fe)
1 /*
2  * QEMU PowerPC XIVE2 interrupt controller model  (POWER10)
3  *
4  * Copyright (c) 2019-2022, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  *
9  */
10 
11 #ifndef PPC_XIVE2_H
12 #define PPC_XIVE2_H
13 
14 #include "hw/ppc/xive2_regs.h"
15 
16 /*
17  * XIVE2 Router (POWER10)
18  */
19 typedef struct Xive2Router {
20     SysBusDevice    parent;
21 
22     XiveFabric *xfb;
23 } Xive2Router;
24 
25 #define TYPE_XIVE2_ROUTER "xive2-router"
26 OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);
27 
28 typedef struct Xive2RouterClass {
29     SysBusDeviceClass parent;
30 
31     /* XIVE table accessors */
32     int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
33                    Xive2Eas *eas);
34     int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
35                    Xive2End *end);
36     int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
37                      Xive2End *end, uint8_t word_number);
38     int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
39                    Xive2Nvp *nvp);
40     int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
41                      Xive2Nvp *nvp, uint8_t word_number);
42     uint8_t (*get_block_id)(Xive2Router *xrtr);
43 } Xive2RouterClass;
44 
45 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
46                         Xive2Eas *eas);
47 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
48                         Xive2End *end);
49 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
50                           Xive2End *end, uint8_t word_number);
51 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
52                         Xive2Nvp *nvp);
53 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
54                           Xive2Nvp *nvp, uint8_t word_number);
55 
56 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn);
57 
58 /*
59  * XIVE2 Presenter (POWER10)
60  */
61 
62 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
63                                uint8_t format,
64                                uint8_t nvt_blk, uint32_t nvt_idx,
65                                bool cam_ignore, uint32_t logic_serv);
66 
67 /*
68  * XIVE2 END ESBs  (POWER10)
69  */
70 
71 #define TYPE_XIVE2_END_SOURCE "xive2-end-source"
72 OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE)
73 
74 typedef struct Xive2EndSource {
75     DeviceState parent;
76 
77     uint32_t        nr_ends;
78 
79     /* ESB memory region */
80     uint32_t        esb_shift;
81     MemoryRegion    esb_mmio;
82 
83     Xive2Router     *xrtr;
84 } Xive2EndSource;
85 
86 
87 #endif /* PPC_XIVE2_H */
88