1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * 5 * The POWER9 processor comes with a new interrupt controller, called 6 * XIVE as "eXternal Interrupt Virtualization Engine". 7 * 8 * = Overall architecture 9 * 10 * 11 * XIVE Interrupt Controller 12 * +------------------------------------+ IPIs 13 * | +---------+ +---------+ +--------+ | +-------+ 14 * | |VC | |CQ | |PC |----> | CORES | 15 * | | esb | | | | |----> | | 16 * | | eas | | Bridge | | tctx |----> | | 17 * | |SC end | | | | nvt | | | | 18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+ 19 * | RAM | +------------------|-----------------+ | | | 20 * | | | | | | 21 * | | | | | | 22 * | | +--------------------v------------------------v-v-v--+ other 23 * | <--+ Power Bus +--> chips 24 * | esb | +---------+-----------------------+------------------+ 25 * | eas | | | 26 * | end | +--|------+ | 27 * | nvt | +----+----+ | +----+----+ 28 * +------+ |SC | | |SC | 29 * | | | | | 30 * | PQ-bits | | | PQ-bits | 31 * | local |-+ | in VC | 32 * +---------+ +---------+ 33 * PCIe NX,NPU,CAPI 34 * 35 * SC: Source Controller (aka. IVSE) 36 * VC: Virtualization Controller (aka. IVRE) 37 * PC: Presentation Controller (aka. IVPE) 38 * CQ: Common Queue (Bridge) 39 * 40 * PQ-bits: 2 bits source state machine (P:pending Q:queued) 41 * esb: Event State Buffer (Array of PQ bits in an IVSE) 42 * eas: Event Assignment Structure 43 * end: Event Notification Descriptor 44 * nvt: Notification Virtual Target 45 * tctx: Thread interrupt Context 46 * 47 * 48 * The XIVE IC is composed of three sub-engines : 49 * 50 * - Interrupt Virtualization Source Engine (IVSE), or Source 51 * Controller (SC). These are found in PCI PHBs, in the PSI host 52 * bridge controller, but also inside the main controller for the 53 * core IPIs and other sub-chips (NX, CAP, NPU) of the 54 * chip/processor. They are configured to feed the IVRE with events. 55 * 56 * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization 57 * Controller (VC). Its job is to match an event source with an 58 * Event Notification Descriptor (END). 59 * 60 * - Interrupt Virtualization Presentation Engine (IVPE) or 61 * Presentation Controller (PC). It maintains the interrupt context 62 * state of each thread and handles the delivery of the external 63 * exception to the thread. 64 * 65 * In XIVE 1.0, the sub-engines used to be referred as: 66 * 67 * SC Source Controller 68 * VC Virtualization Controller 69 * PC Presentation Controller 70 * CQ Common Queue (PowerBUS Bridge) 71 * 72 * 73 * = XIVE internal tables 74 * 75 * Each of the sub-engines uses a set of tables to redirect exceptions 76 * from event sources to CPU threads. 77 * 78 * +-------+ 79 * User or OS | EQ | 80 * or +------>|entries| 81 * Hypervisor | | .. | 82 * Memory | +-------+ 83 * | ^ 84 * | | 85 * +-------------------------------------------------+ 86 * | | 87 * Hypervisor +------+ +---+--+ +---+--+ +------+ 88 * Memory | ESB | | EAT | | ENDT | | NVTT | 89 * (skiboot) +----+-+ +----+-+ +----+-+ +------+ 90 * ^ | ^ | ^ | ^ 91 * | | | | | | | 92 * +-------------------------------------------------+ 93 * | | | | | | | 94 * | | | | | | | 95 * +----|--|--------|--|--------|--|-+ +-|-----+ +------+ 96 * | | | | | | | | | | tctx| |Thread| 97 * IPI or --> | + v + v + v |---| + .. |-----> | 98 * HW events --> | | | | | | 99 * IVSE | IVRE | | IVPE | +------+ 100 * +---------------------------------+ +-------+ 101 * 102 * 103 * 104 * The IVSE have a 2-bits state machine, P for pending and Q for queued, 105 * for each source that allows events to be triggered. They are stored in 106 * an Event State Buffer (ESB) array and can be controlled by MMIOs. 107 * 108 * If the event is let through, the IVRE looks up in the Event Assignment 109 * Structure (EAS) table for an Event Notification Descriptor (END) 110 * configured for the source. Each Event Notification Descriptor defines 111 * a notification path to a CPU and an in-memory Event Queue, in which 112 * will be enqueued an EQ data for the OS to pull. 113 * 114 * The IVPE determines if a Notification Virtual Target (NVT) can 115 * handle the event by scanning the thread contexts of the VCPUs 116 * dispatched on the processor HW threads. It maintains the state of 117 * the thread interrupt context (TCTX) of each thread in a NVT table. 118 * 119 * = Acronyms 120 * 121 * Description In XIVE 1.0, used to be referred as 122 * 123 * EAS Event Assignment Structure IVE Interrupt Virt. Entry 124 * EAT Event Assignment Table IVT Interrupt Virt. Table 125 * ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table 126 * EQ Event Queue same 127 * ESB Event State Buffer SBE State Bit Entry 128 * NVT Notif. Virtual Target VPD Virtual Processor Desc. 129 * NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table 130 * TCTX Thread interrupt Context 131 * 132 * 133 * Copyright (c) 2017-2018, IBM Corporation. 134 * 135 * This code is licensed under the GPL version 2 or later. See the 136 * COPYING file in the top-level directory. 137 * 138 */ 139 140 #ifndef PPC_XIVE_H 141 #define PPC_XIVE_H 142 143 #include "hw/qdev-core.h" 144 145 /* 146 * XIVE Interrupt Source 147 */ 148 149 #define TYPE_XIVE_SOURCE "xive-source" 150 #define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE) 151 152 /* 153 * XIVE Interrupt Source characteristics, which define how the ESB are 154 * controlled. 155 */ 156 #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */ 157 #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */ 158 159 typedef struct XiveSource { 160 DeviceState parent; 161 162 /* IRQs */ 163 uint32_t nr_irqs; 164 qemu_irq *qirqs; 165 166 /* PQ bits */ 167 uint8_t *status; 168 169 /* ESB memory region */ 170 uint64_t esb_flags; 171 uint32_t esb_shift; 172 MemoryRegion esb_mmio; 173 } XiveSource; 174 175 /* 176 * ESB MMIO setting. Can be one page, for both source triggering and 177 * source management, or two different pages. See below for magic 178 * values. 179 */ 180 #define XIVE_ESB_4K 12 /* PSI HB only */ 181 #define XIVE_ESB_4K_2PAGE 13 182 #define XIVE_ESB_64K 16 183 #define XIVE_ESB_64K_2PAGE 17 184 185 static inline bool xive_source_esb_has_2page(XiveSource *xsrc) 186 { 187 return xsrc->esb_shift == XIVE_ESB_64K_2PAGE || 188 xsrc->esb_shift == XIVE_ESB_4K_2PAGE; 189 } 190 191 /* The trigger page is always the first/even page */ 192 static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno) 193 { 194 assert(srcno < xsrc->nr_irqs); 195 return (1ull << xsrc->esb_shift) * srcno; 196 } 197 198 /* In a two pages ESB MMIO setting, the odd page is for management */ 199 static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno) 200 { 201 hwaddr addr = xive_source_esb_page(xsrc, srcno); 202 203 if (xive_source_esb_has_2page(xsrc)) { 204 addr += (1 << (xsrc->esb_shift - 1)); 205 } 206 207 return addr; 208 } 209 210 /* 211 * Each interrupt source has a 2-bit state machine which can be 212 * controlled by MMIO. P indicates that an interrupt is pending (has 213 * been sent to a queue and is waiting for an EOI). Q indicates that 214 * the interrupt has been triggered while pending. 215 * 216 * This acts as a coalescing mechanism in order to guarantee that a 217 * given interrupt only occurs at most once in a queue. 218 * 219 * When doing an EOI, the Q bit will indicate if the interrupt 220 * needs to be re-triggered. 221 */ 222 #define XIVE_ESB_VAL_P 0x2 223 #define XIVE_ESB_VAL_Q 0x1 224 225 #define XIVE_ESB_RESET 0x0 226 #define XIVE_ESB_PENDING XIVE_ESB_VAL_P 227 #define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q) 228 #define XIVE_ESB_OFF XIVE_ESB_VAL_Q 229 230 /* 231 * "magic" Event State Buffer (ESB) MMIO offsets. 232 * 233 * The following offsets into the ESB MMIO allow to read or manipulate 234 * the PQ bits. They must be used with an 8-byte load instruction. 235 * They all return the previous state of the interrupt (atomically). 236 * 237 * Additionally, some ESB pages support doing an EOI via a store and 238 * some ESBs support doing a trigger via a separate trigger page. 239 */ 240 #define XIVE_ESB_STORE_EOI 0x400 /* Store */ 241 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */ 242 #define XIVE_ESB_GET 0x800 /* Load */ 243 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ 244 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ 245 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ 246 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ 247 248 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno); 249 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq); 250 251 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, 252 Monitor *mon); 253 254 static inline qemu_irq xive_source_qirq(XiveSource *xsrc, uint32_t srcno) 255 { 256 assert(srcno < xsrc->nr_irqs); 257 return xsrc->qirqs[srcno]; 258 } 259 260 #endif /* PPC_XIVE_H */ 261