1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #ifndef XICS_H 29 #define XICS_H 30 31 #include "hw/sysbus.h" 32 33 #define TYPE_XICS_COMMON "xics-common" 34 #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON) 35 36 /* 37 * Retain xics as the type name to be compatible for migration. Rest all the 38 * functions, class and variables are renamed as xics_spapr. 39 */ 40 #define TYPE_XICS_SPAPR "xics" 41 #define XICS_SPAPR(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_SPAPR) 42 43 #define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm" 44 #define XICS_SPAPR_KVM(obj) \ 45 OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM) 46 47 #define XICS_COMMON_CLASS(klass) \ 48 OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON) 49 #define XICS_SPAPR_CLASS(klass) \ 50 OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_SPAPR) 51 #define XICS_COMMON_GET_CLASS(obj) \ 52 OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON) 53 #define XICS_SPAPR_GET_CLASS(obj) \ 54 OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR) 55 56 #define XICS_IPI 0x2 57 #define XICS_BUID 0x1 58 #define XICS_IRQ_BASE (XICS_BUID << 12) 59 60 /* 61 * We currently only support one BUID which is our interrupt base 62 * (the kernel implementation supports more but we don't exploit 63 * that yet) 64 */ 65 typedef struct XICSStateClass XICSStateClass; 66 typedef struct XICSState XICSState; 67 typedef struct ICPStateClass ICPStateClass; 68 typedef struct ICPState ICPState; 69 typedef struct ICSStateClass ICSStateClass; 70 typedef struct ICSState ICSState; 71 typedef struct ICSIRQState ICSIRQState; 72 typedef struct XICSFabric XICSFabric; 73 74 struct XICSStateClass { 75 DeviceClass parent_class; 76 77 void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu); 78 }; 79 80 struct XICSState { 81 /*< private >*/ 82 DeviceState parent_obj; 83 /*< public >*/ 84 uint32_t nr_servers; 85 ICPState *ss; 86 QLIST_HEAD(, ICSState) ics; 87 }; 88 89 #define TYPE_ICP "icp" 90 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) 91 92 #define TYPE_KVM_ICP "icp-kvm" 93 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP) 94 95 #define ICP_CLASS(klass) \ 96 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) 97 #define ICP_GET_CLASS(obj) \ 98 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) 99 100 struct ICPStateClass { 101 DeviceClass parent_class; 102 103 void (*pre_save)(ICPState *s); 104 int (*post_load)(ICPState *s, int version_id); 105 }; 106 107 struct ICPState { 108 /*< private >*/ 109 DeviceState parent_obj; 110 /*< public >*/ 111 CPUState *cs; 112 ICSState *xirr_owner; 113 uint32_t xirr; 114 uint8_t pending_priority; 115 uint8_t mfrr; 116 qemu_irq output; 117 bool cap_irq_xics_enabled; 118 119 XICSFabric *xics; 120 }; 121 122 #define TYPE_ICS_BASE "ics-base" 123 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE) 124 125 /* Retain ics for sPAPR for migration from existing sPAPR guests */ 126 #define TYPE_ICS_SIMPLE "ics" 127 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE) 128 129 #define TYPE_ICS_KVM "icskvm" 130 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM) 131 132 #define ICS_BASE_CLASS(klass) \ 133 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE) 134 #define ICS_BASE_GET_CLASS(obj) \ 135 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE) 136 137 struct ICSStateClass { 138 DeviceClass parent_class; 139 140 void (*realize)(DeviceState *dev, Error **errp); 141 void (*pre_save)(ICSState *s); 142 int (*post_load)(ICSState *s, int version_id); 143 void (*reject)(ICSState *s, uint32_t irq); 144 void (*resend)(ICSState *s); 145 void (*eoi)(ICSState *s, uint32_t irq); 146 }; 147 148 struct ICSState { 149 /*< private >*/ 150 DeviceState parent_obj; 151 /*< public >*/ 152 uint32_t nr_irqs; 153 uint32_t offset; 154 qemu_irq *qirqs; 155 ICSIRQState *irqs; 156 XICSState *xics; 157 QLIST_ENTRY(ICSState) list; 158 }; 159 160 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) 161 { 162 return (ics->offset != 0) && (nr >= ics->offset) 163 && (nr < (ics->offset + ics->nr_irqs)); 164 } 165 166 struct ICSIRQState { 167 uint32_t server; 168 uint8_t priority; 169 uint8_t saved_priority; 170 #define XICS_STATUS_ASSERTED 0x1 171 #define XICS_STATUS_SENT 0x2 172 #define XICS_STATUS_REJECTED 0x4 173 #define XICS_STATUS_MASKED_PENDING 0x8 174 uint8_t status; 175 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */ 176 #define XICS_FLAGS_IRQ_LSI 0x1 177 #define XICS_FLAGS_IRQ_MSI 0x2 178 #define XICS_FLAGS_IRQ_MASK 0x3 179 uint8_t flags; 180 }; 181 182 typedef struct XICSFabric { 183 Object parent; 184 } XICSFabric; 185 186 #define TYPE_XICS_FABRIC "xics-fabric" 187 #define XICS_FABRIC(obj) \ 188 OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC) 189 #define XICS_FABRIC_CLASS(klass) \ 190 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC) 191 #define XICS_FABRIC_GET_CLASS(obj) \ 192 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC) 193 194 typedef struct XICSFabricClass { 195 InterfaceClass parent; 196 ICSState *(*ics_get)(XICSFabric *xi, int irq); 197 void (*ics_resend)(XICSFabric *xi); 198 } XICSFabricClass; 199 200 #define XICS_IRQS_SPAPR 1024 201 202 qemu_irq xics_get_qirq(XICSFabric *xi, int irq); 203 204 int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp); 205 int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align, 206 Error **errp); 207 void spapr_ics_free(ICSState *ics, int irq, int num); 208 void spapr_dt_xics(XICSState *xics, void *fdt, uint32_t phandle); 209 210 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); 211 void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu); 212 213 /* Internal XICS interfaces */ 214 int xics_get_cpu_index_by_dt_id(int cpu_dt_id); 215 216 void icp_set_cppr(ICPState *icp, uint8_t cppr); 217 void icp_set_mfrr(ICPState *icp, uint8_t mfrr); 218 uint32_t icp_accept(ICPState *ss); 219 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr); 220 void icp_eoi(ICPState *icp, uint32_t xirr); 221 222 void ics_simple_write_xive(ICSState *ics, int nr, int server, 223 uint8_t priority, uint8_t saved_priority); 224 225 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); 226 227 void ics_resend(ICSState *ics); 228 229 #endif /* XICS_H */ 230