1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #ifndef XICS_H 29 #define XICS_H 30 31 #include "hw/qdev.h" 32 33 #define XICS_IPI 0x2 34 #define XICS_BUID 0x1 35 #define XICS_IRQ_BASE (XICS_BUID << 12) 36 37 /* 38 * We currently only support one BUID which is our interrupt base 39 * (the kernel implementation supports more but we don't exploit 40 * that yet) 41 */ 42 typedef struct ICPStateClass ICPStateClass; 43 typedef struct ICPState ICPState; 44 typedef struct PnvICPState PnvICPState; 45 typedef struct ICSStateClass ICSStateClass; 46 typedef struct ICSState ICSState; 47 typedef struct ICSIRQState ICSIRQState; 48 typedef struct XICSFabric XICSFabric; 49 typedef struct PowerPCCPU PowerPCCPU; 50 51 #define TYPE_ICP "icp" 52 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) 53 54 #define TYPE_KVM_ICP "icp-kvm" 55 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP) 56 57 #define TYPE_PNV_ICP "pnv-icp" 58 #define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP) 59 60 #define ICP_CLASS(klass) \ 61 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) 62 #define ICP_GET_CLASS(obj) \ 63 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) 64 65 struct ICPStateClass { 66 DeviceClass parent_class; 67 68 void (*realize)(DeviceState *dev, Error **errp); 69 void (*pre_save)(ICPState *s); 70 int (*post_load)(ICPState *s, int version_id); 71 void (*cpu_setup)(ICPState *icp, PowerPCCPU *cpu); 72 }; 73 74 struct ICPState { 75 /*< private >*/ 76 DeviceState parent_obj; 77 /*< public >*/ 78 CPUState *cs; 79 ICSState *xirr_owner; 80 uint32_t xirr; 81 uint8_t pending_priority; 82 uint8_t mfrr; 83 qemu_irq output; 84 bool cap_irq_xics_enabled; 85 86 XICSFabric *xics; 87 }; 88 89 struct PnvICPState { 90 ICPState parent_obj; 91 92 MemoryRegion mmio; 93 uint32_t links[3]; 94 }; 95 96 #define TYPE_ICS_BASE "ics-base" 97 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE) 98 99 /* Retain ics for sPAPR for migration from existing sPAPR guests */ 100 #define TYPE_ICS_SIMPLE "ics" 101 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE) 102 103 #define TYPE_ICS_KVM "icskvm" 104 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM) 105 106 #define ICS_BASE_CLASS(klass) \ 107 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE) 108 #define ICS_BASE_GET_CLASS(obj) \ 109 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE) 110 111 struct ICSStateClass { 112 DeviceClass parent_class; 113 114 void (*realize)(DeviceState *dev, Error **errp); 115 void (*pre_save)(ICSState *s); 116 int (*post_load)(ICSState *s, int version_id); 117 void (*reject)(ICSState *s, uint32_t irq); 118 void (*resend)(ICSState *s); 119 void (*eoi)(ICSState *s, uint32_t irq); 120 }; 121 122 struct ICSState { 123 /*< private >*/ 124 DeviceState parent_obj; 125 /*< public >*/ 126 uint32_t nr_irqs; 127 uint32_t offset; 128 qemu_irq *qirqs; 129 ICSIRQState *irqs; 130 XICSFabric *xics; 131 }; 132 133 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) 134 { 135 return (ics->offset != 0) && (nr >= ics->offset) 136 && (nr < (ics->offset + ics->nr_irqs)); 137 } 138 139 struct ICSIRQState { 140 uint32_t server; 141 uint8_t priority; 142 uint8_t saved_priority; 143 #define XICS_STATUS_ASSERTED 0x1 144 #define XICS_STATUS_SENT 0x2 145 #define XICS_STATUS_REJECTED 0x4 146 #define XICS_STATUS_MASKED_PENDING 0x8 147 uint8_t status; 148 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */ 149 #define XICS_FLAGS_IRQ_LSI 0x1 150 #define XICS_FLAGS_IRQ_MSI 0x2 151 #define XICS_FLAGS_IRQ_MASK 0x3 152 uint8_t flags; 153 }; 154 155 struct XICSFabric { 156 Object parent; 157 }; 158 159 #define TYPE_XICS_FABRIC "xics-fabric" 160 #define XICS_FABRIC(obj) \ 161 OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC) 162 #define XICS_FABRIC_CLASS(klass) \ 163 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC) 164 #define XICS_FABRIC_GET_CLASS(obj) \ 165 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC) 166 167 typedef struct XICSFabricClass { 168 InterfaceClass parent; 169 ICSState *(*ics_get)(XICSFabric *xi, int irq); 170 void (*ics_resend)(XICSFabric *xi); 171 ICPState *(*icp_get)(XICSFabric *xi, int server); 172 } XICSFabricClass; 173 174 #define XICS_IRQS_SPAPR 1024 175 176 int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp); 177 int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align, 178 Error **errp); 179 void spapr_ics_free(ICSState *ics, int irq, int num); 180 void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle); 181 182 qemu_irq xics_get_qirq(XICSFabric *xi, int irq); 183 ICPState *xics_icp_get(XICSFabric *xi, int server); 184 void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp); 185 void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu); 186 187 /* Internal XICS interfaces */ 188 void icp_set_cppr(ICPState *icp, uint8_t cppr); 189 void icp_set_mfrr(ICPState *icp, uint8_t mfrr); 190 uint32_t icp_accept(ICPState *ss); 191 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr); 192 void icp_eoi(ICPState *icp, uint32_t xirr); 193 194 void ics_simple_write_xive(ICSState *ics, int nr, int server, 195 uint8_t priority, uint8_t saved_priority); 196 197 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); 198 void icp_pic_print_info(ICPState *icp, Monitor *mon); 199 void ics_pic_print_info(ICSState *ics, Monitor *mon); 200 201 void ics_resend(ICSState *ics); 202 void icp_resend(ICPState *ss); 203 204 typedef struct sPAPRMachineState sPAPRMachineState; 205 206 int xics_kvm_init(sPAPRMachineState *spapr, Error **errp); 207 int xics_spapr_init(sPAPRMachineState *spapr, Error **errp); 208 209 #endif /* XICS_H */ 210