1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #ifndef XICS_H 29 #define XICS_H 30 31 #include "hw/qdev.h" 32 33 #define XICS_IPI 0x2 34 #define XICS_BUID 0x1 35 #define XICS_IRQ_BASE (XICS_BUID << 12) 36 37 /* 38 * We currently only support one BUID which is our interrupt base 39 * (the kernel implementation supports more but we don't exploit 40 * that yet) 41 */ 42 typedef struct ICPStateClass ICPStateClass; 43 typedef struct ICPState ICPState; 44 typedef struct ICSStateClass ICSStateClass; 45 typedef struct ICSState ICSState; 46 typedef struct ICSIRQState ICSIRQState; 47 typedef struct XICSFabric XICSFabric; 48 49 #define TYPE_ICP "icp" 50 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) 51 52 #define TYPE_KVM_ICP "icp-kvm" 53 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP) 54 55 #define ICP_CLASS(klass) \ 56 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) 57 #define ICP_GET_CLASS(obj) \ 58 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) 59 60 struct ICPStateClass { 61 DeviceClass parent_class; 62 63 void (*realize)(DeviceState *dev, Error **errp); 64 void (*pre_save)(ICPState *s); 65 int (*post_load)(ICPState *s, int version_id); 66 void (*cpu_setup)(ICPState *icp, PowerPCCPU *cpu); 67 }; 68 69 struct ICPState { 70 /*< private >*/ 71 DeviceState parent_obj; 72 /*< public >*/ 73 CPUState *cs; 74 ICSState *xirr_owner; 75 uint32_t xirr; 76 uint8_t pending_priority; 77 uint8_t mfrr; 78 qemu_irq output; 79 bool cap_irq_xics_enabled; 80 81 XICSFabric *xics; 82 }; 83 84 #define TYPE_ICS_BASE "ics-base" 85 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE) 86 87 /* Retain ics for sPAPR for migration from existing sPAPR guests */ 88 #define TYPE_ICS_SIMPLE "ics" 89 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE) 90 91 #define TYPE_ICS_KVM "icskvm" 92 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM) 93 94 #define ICS_BASE_CLASS(klass) \ 95 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE) 96 #define ICS_BASE_GET_CLASS(obj) \ 97 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE) 98 99 struct ICSStateClass { 100 DeviceClass parent_class; 101 102 void (*realize)(DeviceState *dev, Error **errp); 103 void (*pre_save)(ICSState *s); 104 int (*post_load)(ICSState *s, int version_id); 105 void (*reject)(ICSState *s, uint32_t irq); 106 void (*resend)(ICSState *s); 107 void (*eoi)(ICSState *s, uint32_t irq); 108 }; 109 110 struct ICSState { 111 /*< private >*/ 112 DeviceState parent_obj; 113 /*< public >*/ 114 uint32_t nr_irqs; 115 uint32_t offset; 116 qemu_irq *qirqs; 117 ICSIRQState *irqs; 118 XICSFabric *xics; 119 }; 120 121 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) 122 { 123 return (ics->offset != 0) && (nr >= ics->offset) 124 && (nr < (ics->offset + ics->nr_irqs)); 125 } 126 127 struct ICSIRQState { 128 uint32_t server; 129 uint8_t priority; 130 uint8_t saved_priority; 131 #define XICS_STATUS_ASSERTED 0x1 132 #define XICS_STATUS_SENT 0x2 133 #define XICS_STATUS_REJECTED 0x4 134 #define XICS_STATUS_MASKED_PENDING 0x8 135 uint8_t status; 136 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */ 137 #define XICS_FLAGS_IRQ_LSI 0x1 138 #define XICS_FLAGS_IRQ_MSI 0x2 139 #define XICS_FLAGS_IRQ_MASK 0x3 140 uint8_t flags; 141 }; 142 143 struct XICSFabric { 144 Object parent; 145 }; 146 147 #define TYPE_XICS_FABRIC "xics-fabric" 148 #define XICS_FABRIC(obj) \ 149 OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC) 150 #define XICS_FABRIC_CLASS(klass) \ 151 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC) 152 #define XICS_FABRIC_GET_CLASS(obj) \ 153 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC) 154 155 typedef struct XICSFabricClass { 156 InterfaceClass parent; 157 ICSState *(*ics_get)(XICSFabric *xi, int irq); 158 void (*ics_resend)(XICSFabric *xi); 159 ICPState *(*icp_get)(XICSFabric *xi, int server); 160 } XICSFabricClass; 161 162 #define XICS_IRQS_SPAPR 1024 163 164 int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp); 165 int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align, 166 Error **errp); 167 void spapr_ics_free(ICSState *ics, int irq, int num); 168 void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle); 169 170 qemu_irq xics_get_qirq(XICSFabric *xi, int irq); 171 ICPState *xics_icp_get(XICSFabric *xi, int server); 172 void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp); 173 void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu); 174 175 /* Internal XICS interfaces */ 176 void icp_set_cppr(ICPState *icp, uint8_t cppr); 177 void icp_set_mfrr(ICPState *icp, uint8_t mfrr); 178 uint32_t icp_accept(ICPState *ss); 179 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr); 180 void icp_eoi(ICPState *icp, uint32_t xirr); 181 182 void ics_simple_write_xive(ICSState *ics, int nr, int server, 183 uint8_t priority, uint8_t saved_priority); 184 185 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); 186 void icp_pic_print_info(ICPState *icp, Monitor *mon); 187 void ics_pic_print_info(ICSState *ics, Monitor *mon); 188 189 void ics_resend(ICSState *ics); 190 void icp_resend(ICPState *ss); 191 192 typedef struct sPAPRMachineState sPAPRMachineState; 193 194 int xics_kvm_init(sPAPRMachineState *spapr, Error **errp); 195 int xics_spapr_init(sPAPRMachineState *spapr, Error **errp); 196 197 #endif /* XICS_H */ 198