1 /* 2 * QEMU PowerPC sPAPR IRQ backend definitions 3 * 4 * Copyright (c) 2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef HW_SPAPR_IRQ_H 11 #define HW_SPAPR_IRQ_H 12 13 #include "target/ppc/cpu-qom.h" 14 15 /* 16 * IRQ range offsets per device type 17 */ 18 #define SPAPR_IRQ_IPI 0x0 19 20 #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */ 21 #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000) 22 #define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001) 23 #define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */ 24 #define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */ 25 26 /* Offset of the dynamic range covered by the bitmap allocator */ 27 #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300) 28 29 #define SPAPR_NR_XIRQS 0x1000 30 31 typedef struct SpaprMachineState SpaprMachineState; 32 33 typedef struct SpaprInterruptController SpaprInterruptController; 34 35 #define TYPE_SPAPR_INTC "spapr-interrupt-controller" 36 #define SPAPR_INTC(obj) \ 37 INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC) 38 #define SPAPR_INTC_CLASS(klass) \ 39 OBJECT_CLASS_CHECK(SpaprInterruptControllerClass, (klass), TYPE_SPAPR_INTC) 40 #define SPAPR_INTC_GET_CLASS(obj) \ 41 OBJECT_GET_CLASS(SpaprInterruptControllerClass, (obj), TYPE_SPAPR_INTC) 42 43 typedef struct SpaprInterruptControllerClass { 44 InterfaceClass parent; 45 46 int (*activate)(SpaprInterruptController *intc, Error **errp); 47 void (*deactivate)(SpaprInterruptController *intc); 48 49 /* 50 * These methods will typically be called on all intcs, active and 51 * inactive 52 */ 53 int (*cpu_intc_create)(SpaprInterruptController *intc, 54 PowerPCCPU *cpu, Error **errp); 55 int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi, 56 Error **errp); 57 void (*free_irq)(SpaprInterruptController *intc, int irq); 58 59 /* These methods should only be called on the active intc */ 60 void (*set_irq)(SpaprInterruptController *intc, int irq, int val); 61 void (*print_info)(SpaprInterruptController *intc, Monitor *mon); 62 void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers, 63 void *fdt, uint32_t phandle); 64 int (*post_load)(SpaprInterruptController *intc, int version_id); 65 } SpaprInterruptControllerClass; 66 67 void spapr_irq_update_active_intc(SpaprMachineState *spapr); 68 69 int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, 70 PowerPCCPU *cpu, Error **errp); 71 void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon); 72 void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers, 73 void *fdt, uint32_t phandle); 74 75 uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr); 76 int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, 77 Error **errp); 78 void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); 79 80 typedef struct SpaprIrq { 81 bool xics; 82 bool xive; 83 } SpaprIrq; 84 85 extern SpaprIrq spapr_irq_xics; 86 extern SpaprIrq spapr_irq_xics_legacy; 87 extern SpaprIrq spapr_irq_xive; 88 extern SpaprIrq spapr_irq_dual; 89 90 void spapr_irq_init(SpaprMachineState *spapr, Error **errp); 91 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp); 92 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num); 93 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq); 94 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id); 95 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp); 96 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp); 97 int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **), 98 SpaprInterruptController *intc, 99 Error **errp); 100 101 /* 102 * XICS legacy routines 103 */ 104 int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp); 105 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp) 106 107 #endif 108