1 /* 2 * QEMU PowerPC sPAPR IRQ backend definitions 3 * 4 * Copyright (c) 2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef HW_SPAPR_IRQ_H 11 #define HW_SPAPR_IRQ_H 12 13 #include "target/ppc/cpu-qom.h" 14 15 /* 16 * IRQ range offsets per device type 17 */ 18 #define SPAPR_IRQ_IPI 0x0 19 20 #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */ 21 #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000) 22 #define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001) 23 #define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */ 24 #define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */ 25 26 /* Offset of the dynamic range covered by the bitmap allocator */ 27 #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300) 28 29 #define SPAPR_NR_XIRQS 0x1000 30 #define SPAPR_NR_MSIS (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ_MSI) 31 32 typedef struct SpaprMachineState SpaprMachineState; 33 34 typedef struct SpaprInterruptController SpaprInterruptController; 35 36 #define TYPE_SPAPR_INTC "spapr-interrupt-controller" 37 #define SPAPR_INTC(obj) \ 38 INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC) 39 #define SPAPR_INTC_CLASS(klass) \ 40 OBJECT_CLASS_CHECK(SpaprInterruptControllerClass, (klass), TYPE_SPAPR_INTC) 41 #define SPAPR_INTC_GET_CLASS(obj) \ 42 OBJECT_GET_CLASS(SpaprInterruptControllerClass, (obj), TYPE_SPAPR_INTC) 43 44 typedef struct SpaprInterruptControllerClass { 45 InterfaceClass parent; 46 47 int (*activate)(SpaprInterruptController *intc, Error **errp); 48 void (*deactivate)(SpaprInterruptController *intc); 49 50 /* 51 * These methods will typically be called on all intcs, active and 52 * inactive 53 */ 54 int (*cpu_intc_create)(SpaprInterruptController *intc, 55 PowerPCCPU *cpu, Error **errp); 56 int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi, 57 Error **errp); 58 void (*free_irq)(SpaprInterruptController *intc, int irq); 59 60 /* These methods should only be called on the active intc */ 61 void (*set_irq)(SpaprInterruptController *intc, int irq, int val); 62 void (*print_info)(SpaprInterruptController *intc, Monitor *mon); 63 void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers, 64 void *fdt, uint32_t phandle); 65 } SpaprInterruptControllerClass; 66 67 void spapr_irq_update_active_intc(SpaprMachineState *spapr); 68 69 int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, 70 PowerPCCPU *cpu, Error **errp); 71 void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon); 72 void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers, 73 void *fdt, uint32_t phandle); 74 75 void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis); 76 int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, 77 Error **errp); 78 void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); 79 80 typedef struct SpaprIrq { 81 uint32_t nr_xirqs; 82 uint32_t nr_msis; 83 bool xics; 84 bool xive; 85 86 int (*post_load)(SpaprMachineState *spapr, int version_id); 87 void (*reset)(SpaprMachineState *spapr, Error **errp); 88 void (*init_kvm)(SpaprMachineState *spapr, Error **errp); 89 } SpaprIrq; 90 91 extern SpaprIrq spapr_irq_xics; 92 extern SpaprIrq spapr_irq_xics_legacy; 93 extern SpaprIrq spapr_irq_xive; 94 extern SpaprIrq spapr_irq_dual; 95 96 void spapr_irq_init(SpaprMachineState *spapr, Error **errp); 97 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp); 98 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num); 99 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq); 100 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id); 101 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp); 102 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp); 103 104 /* 105 * XICS legacy routines 106 */ 107 int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp); 108 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp) 109 110 #endif 111