xref: /qemu/include/hw/ppc/spapr_irq.h (revision 4ffb7496881ec361deaf1f51c41a933bde3cbf7b)
182cffa2eSCédric Le Goater /*
282cffa2eSCédric Le Goater  * QEMU PowerPC sPAPR IRQ backend definitions
382cffa2eSCédric Le Goater  *
482cffa2eSCédric Le Goater  * Copyright (c) 2018, IBM Corporation.
582cffa2eSCédric Le Goater  *
682cffa2eSCédric Le Goater  * This code is licensed under the GPL version 2 or later. See the
782cffa2eSCédric Le Goater  * COPYING file in the top-level directory.
882cffa2eSCédric Le Goater  */
982cffa2eSCédric Le Goater 
1082cffa2eSCédric Le Goater #ifndef HW_SPAPR_IRQ_H
1182cffa2eSCédric Le Goater #define HW_SPAPR_IRQ_H
1282cffa2eSCédric Le Goater 
13ec150c7eSMarkus Armbruster #include "target/ppc/cpu-qom.h"
14ec150c7eSMarkus Armbruster 
1582cffa2eSCédric Le Goater /*
1682cffa2eSCédric Le Goater  * IRQ range offsets per device type
1782cffa2eSCédric Le Goater  */
18dcc345b6SCédric Le Goater #define SPAPR_IRQ_IPI        0x0
1982cffa2eSCédric Le Goater 
20ad8de986SDavid Gibson #define SPAPR_XIRQ_BASE      XICS_IRQ_BASE /* 0x1000 */
21ad8de986SDavid Gibson #define SPAPR_IRQ_EPOW       (SPAPR_XIRQ_BASE + 0x0000)
22ad8de986SDavid Gibson #define SPAPR_IRQ_HOTPLUG    (SPAPR_XIRQ_BASE + 0x0001)
23ad8de986SDavid Gibson #define SPAPR_IRQ_VIO        (SPAPR_XIRQ_BASE + 0x0100)  /* 256 VIO devices */
24ad8de986SDavid Gibson #define SPAPR_IRQ_PCI_LSI    (SPAPR_XIRQ_BASE + 0x0200)  /* 32+ PHBs devices */
25ad8de986SDavid Gibson 
26ad8de986SDavid Gibson /* Offset of the dynamic range covered by the bitmap allocator */
27ad8de986SDavid Gibson #define SPAPR_IRQ_MSI        (SPAPR_XIRQ_BASE + 0x0300)
28ad8de986SDavid Gibson 
29ad8de986SDavid Gibson #define SPAPR_NR_XIRQS       0x1000
3082cffa2eSCédric Le Goater 
31ce2918cbSDavid Gibson typedef struct SpaprMachineState SpaprMachineState;
3282cffa2eSCédric Le Goater 
33150e25f8SDavid Gibson typedef struct SpaprInterruptController SpaprInterruptController;
34150e25f8SDavid Gibson 
35150e25f8SDavid Gibson #define TYPE_SPAPR_INTC "spapr-interrupt-controller"
36150e25f8SDavid Gibson #define SPAPR_INTC(obj)                                     \
37150e25f8SDavid Gibson     INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC)
38150e25f8SDavid Gibson #define SPAPR_INTC_CLASS(klass)                                     \
39150e25f8SDavid Gibson     OBJECT_CLASS_CHECK(SpaprInterruptControllerClass, (klass), TYPE_SPAPR_INTC)
40150e25f8SDavid Gibson #define SPAPR_INTC_GET_CLASS(obj)                                   \
41150e25f8SDavid Gibson     OBJECT_GET_CLASS(SpaprInterruptControllerClass, (obj), TYPE_SPAPR_INTC)
42150e25f8SDavid Gibson 
43150e25f8SDavid Gibson typedef struct SpaprInterruptControllerClass {
44150e25f8SDavid Gibson     InterfaceClass parent;
45ebd6be08SDavid Gibson 
46*4ffb7496SGreg Kurz     int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers,
47*4ffb7496SGreg Kurz                     Error **errp);
4881106dddSDavid Gibson     void (*deactivate)(SpaprInterruptController *intc);
4981106dddSDavid Gibson 
50ebd6be08SDavid Gibson     /*
51ebd6be08SDavid Gibson      * These methods will typically be called on all intcs, active and
52ebd6be08SDavid Gibson      * inactive
53ebd6be08SDavid Gibson      */
54ebd6be08SDavid Gibson     int (*cpu_intc_create)(SpaprInterruptController *intc,
55ebd6be08SDavid Gibson                             PowerPCCPU *cpu, Error **errp);
56d49e8a9bSCédric Le Goater     void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu);
570990ce6aSGreg Kurz     void (*cpu_intc_destroy)(SpaprInterruptController *intc, PowerPCCPU *cpu);
580b0e52b1SDavid Gibson     int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi,
590b0e52b1SDavid Gibson                      Error **errp);
600b0e52b1SDavid Gibson     void (*free_irq)(SpaprInterruptController *intc, int irq);
617bcdbccaSDavid Gibson 
627bcdbccaSDavid Gibson     /* These methods should only be called on the active intc */
637bcdbccaSDavid Gibson     void (*set_irq)(SpaprInterruptController *intc, int irq, int val);
64328d8eb2SDavid Gibson     void (*print_info)(SpaprInterruptController *intc, Monitor *mon);
6505289273SDavid Gibson     void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers,
6605289273SDavid Gibson                void *fdt, uint32_t phandle);
67605994e5SDavid Gibson     int (*post_load)(SpaprInterruptController *intc, int version_id);
68150e25f8SDavid Gibson } SpaprInterruptControllerClass;
69150e25f8SDavid Gibson 
7081106dddSDavid Gibson void spapr_irq_update_active_intc(SpaprMachineState *spapr);
7181106dddSDavid Gibson 
72ebd6be08SDavid Gibson int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
73ebd6be08SDavid Gibson                               PowerPCCPU *cpu, Error **errp);
74d49e8a9bSCédric Le Goater void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr, PowerPCCPU *cpu);
750990ce6aSGreg Kurz void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu);
76328d8eb2SDavid Gibson void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon);
7705289273SDavid Gibson void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
7805289273SDavid Gibson                   void *fdt, uint32_t phandle);
79ebd6be08SDavid Gibson 
808cbe71ecSDavid Gibson uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr);
81ce2918cbSDavid Gibson int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
8282cffa2eSCédric Le Goater                         Error **errp);
83ce2918cbSDavid Gibson void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
8482cffa2eSCédric Le Goater 
85ce2918cbSDavid Gibson typedef struct SpaprIrq {
86ca62823bSDavid Gibson     bool        xics;
87ca62823bSDavid Gibson     bool        xive;
88ce2918cbSDavid Gibson } SpaprIrq;
89ef01ed9dSCédric Le Goater 
90ce2918cbSDavid Gibson extern SpaprIrq spapr_irq_xics;
91ce2918cbSDavid Gibson extern SpaprIrq spapr_irq_xics_legacy;
92ce2918cbSDavid Gibson extern SpaprIrq spapr_irq_xive;
93ce2918cbSDavid Gibson extern SpaprIrq spapr_irq_dual;
94ef01ed9dSCédric Le Goater 
95ce2918cbSDavid Gibson void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
96ce2918cbSDavid Gibson int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
97ce2918cbSDavid Gibson void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
98ce2918cbSDavid Gibson qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
99ce2918cbSDavid Gibson int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
100ce2918cbSDavid Gibson void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
101ce2918cbSDavid Gibson int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
102*4ffb7496SGreg Kurz 
103*4ffb7496SGreg Kurz typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *,
104*4ffb7496SGreg Kurz                                                uint32_t, Error **);
105*4ffb7496SGreg Kurz 
106*4ffb7496SGreg Kurz int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
107567192d4SDavid Gibson                        SpaprInterruptController *intc,
108*4ffb7496SGreg Kurz                        uint32_t nr_servers,
109567192d4SDavid Gibson                        Error **errp);
110ef01ed9dSCédric Le Goater 
111ef01ed9dSCédric Le Goater /*
112ef01ed9dSCédric Le Goater  * XICS legacy routines
113ef01ed9dSCédric Le Goater  */
114ce2918cbSDavid Gibson int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
115ef01ed9dSCédric Le Goater #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
116ef01ed9dSCédric Le Goater 
11782cffa2eSCédric Le Goater #endif
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