1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 11 struct VIOsPAPRBus; 12 struct sPAPRPHBState; 13 struct sPAPRNVRAM; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 typedef struct sPAPREventSource sPAPREventSource; 16 typedef struct sPAPRPendingHPT sPAPRPendingHPT; 17 18 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 19 #define SPAPR_ENTRY_POINT 0x100 20 21 #define SPAPR_TIMEBASE_FREQ 512000000ULL 22 23 #define TYPE_SPAPR_RTC "spapr-rtc" 24 25 #define SPAPR_RTC(obj) \ 26 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 27 28 typedef struct sPAPRRTCState sPAPRRTCState; 29 struct sPAPRRTCState { 30 /*< private >*/ 31 DeviceState parent_obj; 32 int64_t ns_offset; 33 }; 34 35 typedef struct sPAPRDIMMState sPAPRDIMMState; 36 typedef struct sPAPRMachineClass sPAPRMachineClass; 37 38 #define TYPE_SPAPR_MACHINE "spapr-machine" 39 #define SPAPR_MACHINE(obj) \ 40 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 41 #define SPAPR_MACHINE_GET_CLASS(obj) \ 42 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 43 #define SPAPR_MACHINE_CLASS(klass) \ 44 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 45 46 typedef enum { 47 SPAPR_RESIZE_HPT_DEFAULT = 0, 48 SPAPR_RESIZE_HPT_DISABLED, 49 SPAPR_RESIZE_HPT_ENABLED, 50 SPAPR_RESIZE_HPT_REQUIRED, 51 } sPAPRResizeHPT; 52 53 /** 54 * Capabilities 55 */ 56 57 /* Hardware Transactional Memory */ 58 #define SPAPR_CAP_HTM 0x0000000000000001ULL 59 60 typedef struct sPAPRCapabilities sPAPRCapabilities; 61 struct sPAPRCapabilities { 62 uint64_t mask; 63 }; 64 65 /** 66 * sPAPRMachineClass: 67 */ 68 struct sPAPRMachineClass { 69 /*< private >*/ 70 MachineClass parent_class; 71 72 /*< public >*/ 73 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 74 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 75 bool pre_2_10_has_unused_icps; 76 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 77 uint64_t *buid, hwaddr *pio, 78 hwaddr *mmio32, hwaddr *mmio64, 79 unsigned n_dma, uint32_t *liobns, Error **errp); 80 sPAPRResizeHPT resize_hpt_default; 81 sPAPRCapabilities default_caps; 82 }; 83 84 /** 85 * sPAPRMachineState: 86 */ 87 struct sPAPRMachineState { 88 /*< private >*/ 89 MachineState parent_obj; 90 91 struct VIOsPAPRBus *vio_bus; 92 QLIST_HEAD(, sPAPRPHBState) phbs; 93 struct sPAPRNVRAM *nvram; 94 ICSState *ics; 95 sPAPRRTCState rtc; 96 97 sPAPRResizeHPT resize_hpt; 98 void *htab; 99 uint32_t htab_shift; 100 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 101 sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 102 103 hwaddr rma_size; 104 int vrma_adjust; 105 ssize_t rtas_size; 106 void *rtas_blob; 107 long kernel_size; 108 bool kernel_le; 109 uint32_t initrd_base; 110 long initrd_size; 111 uint64_t rtc_offset; /* Now used only during incoming migration */ 112 struct PPCTimebase tb; 113 bool has_graphics; 114 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 115 116 Notifier epow_notifier; 117 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 118 bool use_hotplug_event_source; 119 sPAPREventSource *event_sources; 120 121 /* ibm,client-architecture-support option negotiation */ 122 bool cas_reboot; 123 bool cas_legacy_guest_workaround; 124 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 125 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 126 uint32_t max_compat_pvr; 127 128 /* Migration state */ 129 int htab_save_index; 130 bool htab_first_pass; 131 int htab_fd; 132 133 /* Pending DIMM unplug cache. It is populated when a LMB 134 * unplug starts. It can be regenerated if a migration 135 * occurs during the unplug process. */ 136 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 137 138 /*< public >*/ 139 char *kvm_type; 140 MemoryHotplugState hotplug_memory; 141 142 const char *icp_type; 143 144 sPAPRCapabilities forced_caps, forbidden_caps; 145 sPAPRCapabilities effective_caps; 146 }; 147 148 #define H_SUCCESS 0 149 #define H_BUSY 1 /* Hardware busy -- retry later */ 150 #define H_CLOSED 2 /* Resource closed */ 151 #define H_NOT_AVAILABLE 3 152 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 153 #define H_PARTIAL 5 154 #define H_IN_PROGRESS 14 /* Kind of like busy */ 155 #define H_PAGE_REGISTERED 15 156 #define H_PARTIAL_STORE 16 157 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 158 #define H_CONTINUE 18 /* Returned from H_Join on success */ 159 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 160 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 161 is a good time to retry */ 162 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 163 is a good time to retry */ 164 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 165 is a good time to retry */ 166 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 167 is a good time to retry */ 168 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 169 is a good time to retry */ 170 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 171 is a good time to retry */ 172 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 173 #define H_HARDWARE -1 /* Hardware error */ 174 #define H_FUNCTION -2 /* Function not supported */ 175 #define H_PRIVILEGE -3 /* Caller not privileged */ 176 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 177 #define H_BAD_MODE -5 /* Illegal msr value */ 178 #define H_PTEG_FULL -6 /* PTEG is full */ 179 #define H_NOT_FOUND -7 /* PTE was not found" */ 180 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 181 #define H_NO_MEM -9 182 #define H_AUTHORITY -10 183 #define H_PERMISSION -11 184 #define H_DROPPED -12 185 #define H_SOURCE_PARM -13 186 #define H_DEST_PARM -14 187 #define H_REMOTE_PARM -15 188 #define H_RESOURCE -16 189 #define H_ADAPTER_PARM -17 190 #define H_RH_PARM -18 191 #define H_RCQ_PARM -19 192 #define H_SCQ_PARM -20 193 #define H_EQ_PARM -21 194 #define H_RT_PARM -22 195 #define H_ST_PARM -23 196 #define H_SIGT_PARM -24 197 #define H_TOKEN_PARM -25 198 #define H_MLENGTH_PARM -27 199 #define H_MEM_PARM -28 200 #define H_MEM_ACCESS_PARM -29 201 #define H_ATTR_PARM -30 202 #define H_PORT_PARM -31 203 #define H_MCG_PARM -32 204 #define H_VL_PARM -33 205 #define H_TSIZE_PARM -34 206 #define H_TRACE_PARM -35 207 208 #define H_MASK_PARM -37 209 #define H_MCG_FULL -38 210 #define H_ALIAS_EXIST -39 211 #define H_P_COUNTER -40 212 #define H_TABLE_FULL -41 213 #define H_ALT_TABLE -42 214 #define H_MR_CONDITION -43 215 #define H_NOT_ENOUGH_RESOURCES -44 216 #define H_R_STATE -45 217 #define H_RESCINDEND -46 218 #define H_P2 -55 219 #define H_P3 -56 220 #define H_P4 -57 221 #define H_P5 -58 222 #define H_P6 -59 223 #define H_P7 -60 224 #define H_P8 -61 225 #define H_P9 -62 226 #define H_UNSUPPORTED_FLAG -256 227 #define H_MULTI_THREADS_ACTIVE -9005 228 229 230 /* Long Busy is a condition that can be returned by the firmware 231 * when a call cannot be completed now, but the identical call 232 * should be retried later. This prevents calls blocking in the 233 * firmware for long periods of time. Annoyingly the firmware can return 234 * a range of return codes, hinting at how long we should wait before 235 * retrying. If you don't care for the hint, the macro below is a good 236 * way to check for the long_busy return codes 237 */ 238 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 239 && (x <= H_LONG_BUSY_END_RANGE)) 240 241 /* Flags */ 242 #define H_LARGE_PAGE (1ULL<<(63-16)) 243 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 244 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 245 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 246 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 247 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 248 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 249 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 250 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 251 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 252 #define H_ANDCOND (1ULL<<(63-33)) 253 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 254 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 255 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 256 #define H_COPY_PAGE (1ULL<<(63-49)) 257 #define H_N (1ULL<<(63-61)) 258 #define H_PP1 (1ULL<<(63-62)) 259 #define H_PP2 (1ULL<<(63-63)) 260 261 /* Values for 2nd argument to H_SET_MODE */ 262 #define H_SET_MODE_RESOURCE_SET_CIABR 1 263 #define H_SET_MODE_RESOURCE_SET_DAWR 2 264 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 265 #define H_SET_MODE_RESOURCE_LE 4 266 267 /* Flags for H_SET_MODE_RESOURCE_LE */ 268 #define H_SET_MODE_ENDIAN_BIG 0 269 #define H_SET_MODE_ENDIAN_LITTLE 1 270 271 /* VASI States */ 272 #define H_VASI_INVALID 0 273 #define H_VASI_ENABLED 1 274 #define H_VASI_ABORTED 2 275 #define H_VASI_SUSPENDING 3 276 #define H_VASI_SUSPENDED 4 277 #define H_VASI_RESUMED 5 278 #define H_VASI_COMPLETED 6 279 280 /* DABRX flags */ 281 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 282 #define H_DABRX_KERNEL (1ULL<<(63-62)) 283 #define H_DABRX_USER (1ULL<<(63-63)) 284 285 /* Each control block has to be on a 4K boundary */ 286 #define H_CB_ALIGNMENT 4096 287 288 /* pSeries hypervisor opcodes */ 289 #define H_REMOVE 0x04 290 #define H_ENTER 0x08 291 #define H_READ 0x0c 292 #define H_CLEAR_MOD 0x10 293 #define H_CLEAR_REF 0x14 294 #define H_PROTECT 0x18 295 #define H_GET_TCE 0x1c 296 #define H_PUT_TCE 0x20 297 #define H_SET_SPRG0 0x24 298 #define H_SET_DABR 0x28 299 #define H_PAGE_INIT 0x2c 300 #define H_SET_ASR 0x30 301 #define H_ASR_ON 0x34 302 #define H_ASR_OFF 0x38 303 #define H_LOGICAL_CI_LOAD 0x3c 304 #define H_LOGICAL_CI_STORE 0x40 305 #define H_LOGICAL_CACHE_LOAD 0x44 306 #define H_LOGICAL_CACHE_STORE 0x48 307 #define H_LOGICAL_ICBI 0x4c 308 #define H_LOGICAL_DCBF 0x50 309 #define H_GET_TERM_CHAR 0x54 310 #define H_PUT_TERM_CHAR 0x58 311 #define H_REAL_TO_LOGICAL 0x5c 312 #define H_HYPERVISOR_DATA 0x60 313 #define H_EOI 0x64 314 #define H_CPPR 0x68 315 #define H_IPI 0x6c 316 #define H_IPOLL 0x70 317 #define H_XIRR 0x74 318 #define H_PERFMON 0x7c 319 #define H_MIGRATE_DMA 0x78 320 #define H_REGISTER_VPA 0xDC 321 #define H_CEDE 0xE0 322 #define H_CONFER 0xE4 323 #define H_PROD 0xE8 324 #define H_GET_PPP 0xEC 325 #define H_SET_PPP 0xF0 326 #define H_PURR 0xF4 327 #define H_PIC 0xF8 328 #define H_REG_CRQ 0xFC 329 #define H_FREE_CRQ 0x100 330 #define H_VIO_SIGNAL 0x104 331 #define H_SEND_CRQ 0x108 332 #define H_COPY_RDMA 0x110 333 #define H_REGISTER_LOGICAL_LAN 0x114 334 #define H_FREE_LOGICAL_LAN 0x118 335 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 336 #define H_SEND_LOGICAL_LAN 0x120 337 #define H_BULK_REMOVE 0x124 338 #define H_MULTICAST_CTRL 0x130 339 #define H_SET_XDABR 0x134 340 #define H_STUFF_TCE 0x138 341 #define H_PUT_TCE_INDIRECT 0x13C 342 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 343 #define H_VTERM_PARTNER_INFO 0x150 344 #define H_REGISTER_VTERM 0x154 345 #define H_FREE_VTERM 0x158 346 #define H_RESET_EVENTS 0x15C 347 #define H_ALLOC_RESOURCE 0x160 348 #define H_FREE_RESOURCE 0x164 349 #define H_MODIFY_QP 0x168 350 #define H_QUERY_QP 0x16C 351 #define H_REREGISTER_PMR 0x170 352 #define H_REGISTER_SMR 0x174 353 #define H_QUERY_MR 0x178 354 #define H_QUERY_MW 0x17C 355 #define H_QUERY_HCA 0x180 356 #define H_QUERY_PORT 0x184 357 #define H_MODIFY_PORT 0x188 358 #define H_DEFINE_AQP1 0x18C 359 #define H_GET_TRACE_BUFFER 0x190 360 #define H_DEFINE_AQP0 0x194 361 #define H_RESIZE_MR 0x198 362 #define H_ATTACH_MCQP 0x19C 363 #define H_DETACH_MCQP 0x1A0 364 #define H_CREATE_RPT 0x1A4 365 #define H_REMOVE_RPT 0x1A8 366 #define H_REGISTER_RPAGES 0x1AC 367 #define H_DISABLE_AND_GETC 0x1B0 368 #define H_ERROR_DATA 0x1B4 369 #define H_GET_HCA_INFO 0x1B8 370 #define H_GET_PERF_COUNT 0x1BC 371 #define H_MANAGE_TRACE 0x1C0 372 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 373 #define H_QUERY_INT_STATE 0x1E4 374 #define H_POLL_PENDING 0x1D8 375 #define H_ILLAN_ATTRIBUTES 0x244 376 #define H_MODIFY_HEA_QP 0x250 377 #define H_QUERY_HEA_QP 0x254 378 #define H_QUERY_HEA 0x258 379 #define H_QUERY_HEA_PORT 0x25C 380 #define H_MODIFY_HEA_PORT 0x260 381 #define H_REG_BCMC 0x264 382 #define H_DEREG_BCMC 0x268 383 #define H_REGISTER_HEA_RPAGES 0x26C 384 #define H_DISABLE_AND_GET_HEA 0x270 385 #define H_GET_HEA_INFO 0x274 386 #define H_ALLOC_HEA_RESOURCE 0x278 387 #define H_ADD_CONN 0x284 388 #define H_DEL_CONN 0x288 389 #define H_JOIN 0x298 390 #define H_VASI_STATE 0x2A4 391 #define H_ENABLE_CRQ 0x2B0 392 #define H_GET_EM_PARMS 0x2B8 393 #define H_SET_MPP 0x2D0 394 #define H_GET_MPP 0x2D4 395 #define H_XIRR_X 0x2FC 396 #define H_RANDOM 0x300 397 #define H_SET_MODE 0x31C 398 #define H_RESIZE_HPT_PREPARE 0x36C 399 #define H_RESIZE_HPT_COMMIT 0x370 400 #define H_CLEAN_SLB 0x374 401 #define H_INVALIDATE_PID 0x378 402 #define H_REGISTER_PROC_TBL 0x37C 403 #define H_SIGNAL_SYS_RESET 0x380 404 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET 405 406 /* The hcalls above are standardized in PAPR and implemented by pHyp 407 * as well. 408 * 409 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 410 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 411 * for "platform-specific" hcalls. 412 */ 413 #define KVMPPC_HCALL_BASE 0xf000 414 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 415 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 416 /* Client Architecture support */ 417 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 418 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 419 420 typedef struct sPAPRDeviceTreeUpdateHeader { 421 uint32_t version_id; 422 } sPAPRDeviceTreeUpdateHeader; 423 424 #define hcall_dprintf(fmt, ...) \ 425 do { \ 426 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 427 } while (0) 428 429 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 430 target_ulong opcode, 431 target_ulong *args); 432 433 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 434 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 435 target_ulong *args); 436 437 /* ibm,set-eeh-option */ 438 #define RTAS_EEH_DISABLE 0 439 #define RTAS_EEH_ENABLE 1 440 #define RTAS_EEH_THAW_IO 2 441 #define RTAS_EEH_THAW_DMA 3 442 443 /* ibm,get-config-addr-info2 */ 444 #define RTAS_GET_PE_ADDR 0 445 #define RTAS_GET_PE_MODE 1 446 #define RTAS_PE_MODE_NONE 0 447 #define RTAS_PE_MODE_NOT_SHARED 1 448 #define RTAS_PE_MODE_SHARED 2 449 450 /* ibm,read-slot-reset-state2 */ 451 #define RTAS_EEH_PE_STATE_NORMAL 0 452 #define RTAS_EEH_PE_STATE_RESET 1 453 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 454 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 455 #define RTAS_EEH_PE_STATE_UNAVAIL 5 456 #define RTAS_EEH_NOT_SUPPORT 0 457 #define RTAS_EEH_SUPPORT 1 458 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 459 #define RTAS_EEH_PE_RECOVER_INFO 0 460 461 /* ibm,set-slot-reset */ 462 #define RTAS_SLOT_RESET_DEACTIVATE 0 463 #define RTAS_SLOT_RESET_HOT 1 464 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 465 466 /* ibm,slot-error-detail */ 467 #define RTAS_SLOT_TEMP_ERR_LOG 1 468 #define RTAS_SLOT_PERM_ERR_LOG 2 469 470 /* RTAS return codes */ 471 #define RTAS_OUT_SUCCESS 0 472 #define RTAS_OUT_NO_ERRORS_FOUND 1 473 #define RTAS_OUT_HW_ERROR -1 474 #define RTAS_OUT_BUSY -2 475 #define RTAS_OUT_PARAM_ERROR -3 476 #define RTAS_OUT_NOT_SUPPORTED -3 477 #define RTAS_OUT_NO_SUCH_INDICATOR -3 478 #define RTAS_OUT_NOT_AUTHORIZED -9002 479 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 480 481 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 482 #define RTAS_DDW_PGSIZE_4K 0x01 483 #define RTAS_DDW_PGSIZE_64K 0x02 484 #define RTAS_DDW_PGSIZE_16M 0x04 485 #define RTAS_DDW_PGSIZE_32M 0x08 486 #define RTAS_DDW_PGSIZE_64M 0x10 487 #define RTAS_DDW_PGSIZE_128M 0x20 488 #define RTAS_DDW_PGSIZE_256M 0x40 489 #define RTAS_DDW_PGSIZE_16G 0x80 490 491 /* RTAS tokens */ 492 #define RTAS_TOKEN_BASE 0x2000 493 494 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 495 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 496 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 497 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 498 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 499 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 500 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 501 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 502 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 503 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 504 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 505 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 506 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 507 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 508 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 509 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 510 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 511 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 512 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 513 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 514 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 515 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 516 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 517 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 518 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 519 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 520 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 521 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 522 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 523 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 524 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 525 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 526 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 527 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 528 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 529 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 530 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 531 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 532 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 533 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 534 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 535 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 536 537 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 538 539 /* RTAS ibm,get-system-parameter token values */ 540 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 541 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 542 #define RTAS_SYSPARM_UUID 48 543 544 /* RTAS indicator/sensor types 545 * 546 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 547 * 548 * NOTE: currently only DR-related sensors are implemented here 549 */ 550 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 551 #define RTAS_SENSOR_TYPE_DR 9002 552 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 553 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 554 555 /* Possible values for the platform-processor-diagnostics-run-mode parameter 556 * of the RTAS ibm,get-system-parameter call. 557 */ 558 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 559 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 560 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 561 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 562 563 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 564 { 565 return addr & ~0xF000000000000000ULL; 566 } 567 568 static inline uint32_t rtas_ld(target_ulong phys, int n) 569 { 570 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 571 } 572 573 static inline uint64_t rtas_ldq(target_ulong phys, int n) 574 { 575 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 576 } 577 578 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 579 { 580 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 581 } 582 583 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 584 uint32_t token, 585 uint32_t nargs, target_ulong args, 586 uint32_t nret, target_ulong rets); 587 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 588 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 589 uint32_t token, uint32_t nargs, target_ulong args, 590 uint32_t nret, target_ulong rets); 591 void spapr_dt_rtas_tokens(void *fdt, int rtas); 592 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 593 594 #define SPAPR_TCE_PAGE_SHIFT 12 595 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 596 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 597 598 #define SPAPR_VIO_BASE_LIOBN 0x00000000 599 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 600 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 601 (0x80000000 | ((phb_index) << 8) | (window_num)) 602 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 603 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 604 605 #define RTAS_ERROR_LOG_MAX 2048 606 607 #define RTAS_EVENT_SCAN_RATE 1 608 609 /* This helper should be used to encode interrupt specifiers when the related 610 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 611 * VIO devices, RTAS event sources and PHBs). 612 */ 613 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi) 614 { 615 intspec[0] = cpu_to_be32(irq); 616 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 617 } 618 619 typedef struct sPAPRTCETable sPAPRTCETable; 620 621 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 622 #define SPAPR_TCE_TABLE(obj) \ 623 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 624 625 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 626 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 627 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 628 629 struct sPAPRTCETable { 630 DeviceState parent; 631 uint32_t liobn; 632 uint32_t nb_table; 633 uint64_t bus_offset; 634 uint32_t page_shift; 635 uint64_t *table; 636 uint32_t mig_nb_table; 637 uint64_t *mig_table; 638 bool bypass; 639 bool need_vfio; 640 int fd; 641 MemoryRegion root; 642 IOMMUMemoryRegion iommu; 643 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 644 QLIST_ENTRY(sPAPRTCETable) list; 645 }; 646 647 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 648 649 struct sPAPREventLogEntry { 650 uint32_t summary; 651 uint32_t extended_length; 652 void *extended_log; 653 QTAILQ_ENTRY(sPAPREventLogEntry) next; 654 }; 655 656 void spapr_events_init(sPAPRMachineState *sm); 657 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 658 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 659 target_ulong addr, target_ulong size, 660 sPAPROptionVector *ov5_updates); 661 void close_htab_fd(sPAPRMachineState *spapr); 662 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 663 void spapr_free_hpt(sPAPRMachineState *spapr); 664 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 665 void spapr_tce_table_enable(sPAPRTCETable *tcet, 666 uint32_t page_shift, uint64_t bus_offset, 667 uint32_t nb_table); 668 void spapr_tce_table_disable(sPAPRTCETable *tcet); 669 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 670 671 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 672 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 673 uint32_t liobn, uint64_t window, uint32_t size); 674 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 675 sPAPRTCETable *tcet); 676 void spapr_pci_switch_vga(bool big_endian); 677 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 678 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 679 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 680 uint32_t count); 681 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 682 uint32_t count); 683 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 684 uint32_t count, uint32_t index); 685 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 686 uint32_t count, uint32_t index); 687 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 688 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 689 Error **errp); 690 void spapr_clear_pending_events(sPAPRMachineState *spapr); 691 692 /* CPU and LMB DRC release callbacks. */ 693 void spapr_core_release(DeviceState *dev); 694 void spapr_lmb_release(DeviceState *dev); 695 696 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 697 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 698 699 #define TYPE_SPAPR_RNG "spapr-rng" 700 701 int spapr_rng_populate_dt(void *fdt); 702 703 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 704 705 /* 706 * This defines the maximum number of DIMM slots we can have for sPAPR 707 * guest. This is not defined by sPAPR but we are defining it to 32 slots 708 * based on default number of slots provided by PowerPC kernel. 709 */ 710 #define SPAPR_MAX_RAM_SLOTS 32 711 712 /* 1GB alignment for hotplug memory region */ 713 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 714 715 /* 716 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 717 * property under ibm,dynamic-reconfiguration-memory node. 718 */ 719 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 720 721 /* 722 * Defines for flag value in ibm,dynamic-memory property under 723 * ibm,dynamic-reconfiguration-memory node. 724 */ 725 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 726 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 727 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 728 729 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 730 731 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 732 733 int spapr_vcpu_id(PowerPCCPU *cpu); 734 PowerPCCPU *spapr_find_cpu(int vcpu_id); 735 736 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 737 Error **errp); 738 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 739 bool align, Error **errp); 740 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); 741 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); 742 743 /* 744 * Handling of optional capabilities 745 */ 746 static inline sPAPRCapabilities spapr_caps(uint64_t mask) 747 { 748 sPAPRCapabilities caps = { mask }; 749 return caps; 750 } 751 752 static inline bool spapr_has_cap(sPAPRMachineState *spapr, uint64_t cap) 753 { 754 return !!(spapr->effective_caps.mask & cap); 755 } 756 757 void spapr_caps_reset(sPAPRMachineState *spapr); 758 void spapr_caps_validate(sPAPRMachineState *spapr, Error **errp); 759 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); 760 761 #endif /* HW_SPAPR_H */ 762