1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 12 #include "hw/ppc/xics.h" /* For ICSState */ 13 #include "hw/ppc/spapr_tpm_proxy.h" 14 15 struct SpaprVioBus; 16 struct SpaprPhbState; 17 struct SpaprNvram; 18 19 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 20 typedef struct SpaprEventSource SpaprEventSource; 21 typedef struct SpaprPendingHpt SpaprPendingHpt; 22 23 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 24 #define SPAPR_ENTRY_POINT 0x100 25 26 #define SPAPR_TIMEBASE_FREQ 512000000ULL 27 28 #define TYPE_SPAPR_RTC "spapr-rtc" 29 30 #define SPAPR_RTC(obj) \ 31 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 32 33 typedef struct SpaprRtcState SpaprRtcState; 34 struct SpaprRtcState { 35 /*< private >*/ 36 DeviceState parent_obj; 37 int64_t ns_offset; 38 }; 39 40 typedef struct SpaprDimmState SpaprDimmState; 41 typedef struct SpaprMachineClass SpaprMachineClass; 42 43 #define TYPE_SPAPR_MACHINE "spapr-machine" 44 #define SPAPR_MACHINE(obj) \ 45 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 46 #define SPAPR_MACHINE_GET_CLASS(obj) \ 47 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 48 #define SPAPR_MACHINE_CLASS(klass) \ 49 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 50 51 typedef enum { 52 SPAPR_RESIZE_HPT_DEFAULT = 0, 53 SPAPR_RESIZE_HPT_DISABLED, 54 SPAPR_RESIZE_HPT_ENABLED, 55 SPAPR_RESIZE_HPT_REQUIRED, 56 } SpaprResizeHpt; 57 58 /** 59 * Capabilities 60 */ 61 62 /* Hardware Transactional Memory */ 63 #define SPAPR_CAP_HTM 0x00 64 /* Vector Scalar Extensions */ 65 #define SPAPR_CAP_VSX 0x01 66 /* Decimal Floating Point */ 67 #define SPAPR_CAP_DFP 0x02 68 /* Cache Flush on Privilege Change */ 69 #define SPAPR_CAP_CFPC 0x03 70 /* Speculation Barrier Bounds Checking */ 71 #define SPAPR_CAP_SBBC 0x04 72 /* Indirect Branch Serialisation */ 73 #define SPAPR_CAP_IBS 0x05 74 /* HPT Maximum Page Size (encoded as a shift) */ 75 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 76 /* Nested KVM-HV */ 77 #define SPAPR_CAP_NESTED_KVM_HV 0x07 78 /* Large Decrementer */ 79 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 80 /* Count Cache Flush Assist HW Instruction */ 81 #define SPAPR_CAP_CCF_ASSIST 0x09 82 /* Implements PAPR FWNMI option */ 83 #define SPAPR_CAP_FWNMI 0x0A 84 /* Num Caps */ 85 #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1) 86 87 /* 88 * Capability Values 89 */ 90 /* Bool Caps */ 91 #define SPAPR_CAP_OFF 0x00 92 #define SPAPR_CAP_ON 0x01 93 94 /* Custom Caps */ 95 96 /* Generic */ 97 #define SPAPR_CAP_BROKEN 0x00 98 #define SPAPR_CAP_WORKAROUND 0x01 99 #define SPAPR_CAP_FIXED 0x02 100 /* SPAPR_CAP_IBS (cap-ibs) */ 101 #define SPAPR_CAP_FIXED_IBS 0x02 102 #define SPAPR_CAP_FIXED_CCD 0x03 103 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 104 105 typedef struct SpaprCapabilities SpaprCapabilities; 106 struct SpaprCapabilities { 107 uint8_t caps[SPAPR_CAP_NUM]; 108 }; 109 110 /** 111 * SpaprMachineClass: 112 */ 113 struct SpaprMachineClass { 114 /*< private >*/ 115 MachineClass parent_class; 116 117 /*< public >*/ 118 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 119 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 120 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 121 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 122 bool pre_2_10_has_unused_icps; 123 bool legacy_irq_allocation; 124 uint32_t nr_xirqs; 125 bool broken_host_serial_model; /* present real host info to the guest */ 126 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 127 bool linux_pci_probe; 128 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 129 hwaddr rma_limit; /* clamp the RMA to this size */ 130 131 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 132 uint64_t *buid, hwaddr *pio, 133 hwaddr *mmio32, hwaddr *mmio64, 134 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 135 hwaddr *nv2atsd, Error **errp); 136 SpaprResizeHpt resize_hpt_default; 137 SpaprCapabilities default_caps; 138 SpaprIrq *irq; 139 }; 140 141 /** 142 * SpaprMachineState: 143 */ 144 struct SpaprMachineState { 145 /*< private >*/ 146 MachineState parent_obj; 147 148 struct SpaprVioBus *vio_bus; 149 QLIST_HEAD(, SpaprPhbState) phbs; 150 struct SpaprNvram *nvram; 151 SpaprRtcState rtc; 152 153 SpaprResizeHpt resize_hpt; 154 void *htab; 155 uint32_t htab_shift; 156 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 157 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 158 159 hwaddr rma_size; 160 uint32_t fdt_size; 161 uint32_t fdt_initial_size; 162 void *fdt_blob; 163 long kernel_size; 164 bool kernel_le; 165 uint64_t kernel_addr; 166 uint32_t initrd_base; 167 long initrd_size; 168 uint64_t rtc_offset; /* Now used only during incoming migration */ 169 struct PPCTimebase tb; 170 bool has_graphics; 171 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 172 173 Notifier epow_notifier; 174 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 175 bool use_hotplug_event_source; 176 SpaprEventSource *event_sources; 177 178 /* ibm,client-architecture-support option negotiation */ 179 bool cas_reboot; 180 bool cas_pre_isa3_guest; 181 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 182 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 183 uint32_t max_compat_pvr; 184 185 /* Migration state */ 186 int htab_save_index; 187 bool htab_first_pass; 188 int htab_fd; 189 190 /* Pending DIMM unplug cache. It is populated when a LMB 191 * unplug starts. It can be regenerated if a migration 192 * occurs during the unplug process. */ 193 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 194 195 /* State related to FWNMI option */ 196 197 /* Machine Check Notification Routine address 198 * registered by "ibm,nmi-register" RTAS call. 199 */ 200 target_ulong fwnmi_machine_check_addr; 201 202 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 203 * set to -1 if a FWNMI machine check is not in progress, else is set to 204 * the CPU that was delivered the machine check, and is set back to -1 205 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 206 * to synchronize other CPUs. 207 */ 208 int fwnmi_machine_check_interlock; 209 QemuCond fwnmi_machine_check_interlock_cond; 210 211 /*< public >*/ 212 char *kvm_type; 213 char *host_model; 214 char *host_serial; 215 216 int32_t irq_map_nr; 217 unsigned long *irq_map; 218 SpaprIrq *irq; 219 qemu_irq *qirqs; 220 SpaprInterruptController *active_intc; 221 ICSState *ics; 222 SpaprXive *xive; 223 224 bool cmd_line_caps[SPAPR_CAP_NUM]; 225 SpaprCapabilities def, eff, mig; 226 227 unsigned gpu_numa_id; 228 SpaprTpmProxy *tpm_proxy; 229 230 Error *fwnmi_migration_blocker; 231 }; 232 233 #define H_SUCCESS 0 234 #define H_BUSY 1 /* Hardware busy -- retry later */ 235 #define H_CLOSED 2 /* Resource closed */ 236 #define H_NOT_AVAILABLE 3 237 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 238 #define H_PARTIAL 5 239 #define H_IN_PROGRESS 14 /* Kind of like busy */ 240 #define H_PAGE_REGISTERED 15 241 #define H_PARTIAL_STORE 16 242 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 243 #define H_CONTINUE 18 /* Returned from H_Join on success */ 244 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 245 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 246 is a good time to retry */ 247 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 248 is a good time to retry */ 249 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 250 is a good time to retry */ 251 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 252 is a good time to retry */ 253 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 254 is a good time to retry */ 255 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 256 is a good time to retry */ 257 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 258 #define H_HARDWARE -1 /* Hardware error */ 259 #define H_FUNCTION -2 /* Function not supported */ 260 #define H_PRIVILEGE -3 /* Caller not privileged */ 261 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 262 #define H_BAD_MODE -5 /* Illegal msr value */ 263 #define H_PTEG_FULL -6 /* PTEG is full */ 264 #define H_NOT_FOUND -7 /* PTE was not found" */ 265 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 266 #define H_NO_MEM -9 267 #define H_AUTHORITY -10 268 #define H_PERMISSION -11 269 #define H_DROPPED -12 270 #define H_SOURCE_PARM -13 271 #define H_DEST_PARM -14 272 #define H_REMOTE_PARM -15 273 #define H_RESOURCE -16 274 #define H_ADAPTER_PARM -17 275 #define H_RH_PARM -18 276 #define H_RCQ_PARM -19 277 #define H_SCQ_PARM -20 278 #define H_EQ_PARM -21 279 #define H_RT_PARM -22 280 #define H_ST_PARM -23 281 #define H_SIGT_PARM -24 282 #define H_TOKEN_PARM -25 283 #define H_MLENGTH_PARM -27 284 #define H_MEM_PARM -28 285 #define H_MEM_ACCESS_PARM -29 286 #define H_ATTR_PARM -30 287 #define H_PORT_PARM -31 288 #define H_MCG_PARM -32 289 #define H_VL_PARM -33 290 #define H_TSIZE_PARM -34 291 #define H_TRACE_PARM -35 292 293 #define H_MASK_PARM -37 294 #define H_MCG_FULL -38 295 #define H_ALIAS_EXIST -39 296 #define H_P_COUNTER -40 297 #define H_TABLE_FULL -41 298 #define H_ALT_TABLE -42 299 #define H_MR_CONDITION -43 300 #define H_NOT_ENOUGH_RESOURCES -44 301 #define H_R_STATE -45 302 #define H_RESCINDEND -46 303 #define H_P2 -55 304 #define H_P3 -56 305 #define H_P4 -57 306 #define H_P5 -58 307 #define H_P6 -59 308 #define H_P7 -60 309 #define H_P8 -61 310 #define H_P9 -62 311 #define H_OVERLAP -68 312 #define H_UNSUPPORTED_FLAG -256 313 #define H_MULTI_THREADS_ACTIVE -9005 314 315 316 /* Long Busy is a condition that can be returned by the firmware 317 * when a call cannot be completed now, but the identical call 318 * should be retried later. This prevents calls blocking in the 319 * firmware for long periods of time. Annoyingly the firmware can return 320 * a range of return codes, hinting at how long we should wait before 321 * retrying. If you don't care for the hint, the macro below is a good 322 * way to check for the long_busy return codes 323 */ 324 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 325 && (x <= H_LONG_BUSY_END_RANGE)) 326 327 /* Flags */ 328 #define H_LARGE_PAGE (1ULL<<(63-16)) 329 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 330 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 331 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 332 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 333 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 334 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 335 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 336 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 337 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 338 #define H_ANDCOND (1ULL<<(63-33)) 339 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 340 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 341 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 342 #define H_COPY_PAGE (1ULL<<(63-49)) 343 #define H_N (1ULL<<(63-61)) 344 #define H_PP1 (1ULL<<(63-62)) 345 #define H_PP2 (1ULL<<(63-63)) 346 347 /* Values for 2nd argument to H_SET_MODE */ 348 #define H_SET_MODE_RESOURCE_SET_CIABR 1 349 #define H_SET_MODE_RESOURCE_SET_DAWR 2 350 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 351 #define H_SET_MODE_RESOURCE_LE 4 352 353 /* Flags for H_SET_MODE_RESOURCE_LE */ 354 #define H_SET_MODE_ENDIAN_BIG 0 355 #define H_SET_MODE_ENDIAN_LITTLE 1 356 357 /* VASI States */ 358 #define H_VASI_INVALID 0 359 #define H_VASI_ENABLED 1 360 #define H_VASI_ABORTED 2 361 #define H_VASI_SUSPENDING 3 362 #define H_VASI_SUSPENDED 4 363 #define H_VASI_RESUMED 5 364 #define H_VASI_COMPLETED 6 365 366 /* DABRX flags */ 367 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 368 #define H_DABRX_KERNEL (1ULL<<(63-62)) 369 #define H_DABRX_USER (1ULL<<(63-63)) 370 371 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 372 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 373 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 374 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 375 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 376 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 377 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 378 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 379 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 380 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 381 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 382 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 383 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 384 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 385 386 /* Each control block has to be on a 4K boundary */ 387 #define H_CB_ALIGNMENT 4096 388 389 /* pSeries hypervisor opcodes */ 390 #define H_REMOVE 0x04 391 #define H_ENTER 0x08 392 #define H_READ 0x0c 393 #define H_CLEAR_MOD 0x10 394 #define H_CLEAR_REF 0x14 395 #define H_PROTECT 0x18 396 #define H_GET_TCE 0x1c 397 #define H_PUT_TCE 0x20 398 #define H_SET_SPRG0 0x24 399 #define H_SET_DABR 0x28 400 #define H_PAGE_INIT 0x2c 401 #define H_SET_ASR 0x30 402 #define H_ASR_ON 0x34 403 #define H_ASR_OFF 0x38 404 #define H_LOGICAL_CI_LOAD 0x3c 405 #define H_LOGICAL_CI_STORE 0x40 406 #define H_LOGICAL_CACHE_LOAD 0x44 407 #define H_LOGICAL_CACHE_STORE 0x48 408 #define H_LOGICAL_ICBI 0x4c 409 #define H_LOGICAL_DCBF 0x50 410 #define H_GET_TERM_CHAR 0x54 411 #define H_PUT_TERM_CHAR 0x58 412 #define H_REAL_TO_LOGICAL 0x5c 413 #define H_HYPERVISOR_DATA 0x60 414 #define H_EOI 0x64 415 #define H_CPPR 0x68 416 #define H_IPI 0x6c 417 #define H_IPOLL 0x70 418 #define H_XIRR 0x74 419 #define H_PERFMON 0x7c 420 #define H_MIGRATE_DMA 0x78 421 #define H_REGISTER_VPA 0xDC 422 #define H_CEDE 0xE0 423 #define H_CONFER 0xE4 424 #define H_PROD 0xE8 425 #define H_GET_PPP 0xEC 426 #define H_SET_PPP 0xF0 427 #define H_PURR 0xF4 428 #define H_PIC 0xF8 429 #define H_REG_CRQ 0xFC 430 #define H_FREE_CRQ 0x100 431 #define H_VIO_SIGNAL 0x104 432 #define H_SEND_CRQ 0x108 433 #define H_COPY_RDMA 0x110 434 #define H_REGISTER_LOGICAL_LAN 0x114 435 #define H_FREE_LOGICAL_LAN 0x118 436 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 437 #define H_SEND_LOGICAL_LAN 0x120 438 #define H_BULK_REMOVE 0x124 439 #define H_MULTICAST_CTRL 0x130 440 #define H_SET_XDABR 0x134 441 #define H_STUFF_TCE 0x138 442 #define H_PUT_TCE_INDIRECT 0x13C 443 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 444 #define H_VTERM_PARTNER_INFO 0x150 445 #define H_REGISTER_VTERM 0x154 446 #define H_FREE_VTERM 0x158 447 #define H_RESET_EVENTS 0x15C 448 #define H_ALLOC_RESOURCE 0x160 449 #define H_FREE_RESOURCE 0x164 450 #define H_MODIFY_QP 0x168 451 #define H_QUERY_QP 0x16C 452 #define H_REREGISTER_PMR 0x170 453 #define H_REGISTER_SMR 0x174 454 #define H_QUERY_MR 0x178 455 #define H_QUERY_MW 0x17C 456 #define H_QUERY_HCA 0x180 457 #define H_QUERY_PORT 0x184 458 #define H_MODIFY_PORT 0x188 459 #define H_DEFINE_AQP1 0x18C 460 #define H_GET_TRACE_BUFFER 0x190 461 #define H_DEFINE_AQP0 0x194 462 #define H_RESIZE_MR 0x198 463 #define H_ATTACH_MCQP 0x19C 464 #define H_DETACH_MCQP 0x1A0 465 #define H_CREATE_RPT 0x1A4 466 #define H_REMOVE_RPT 0x1A8 467 #define H_REGISTER_RPAGES 0x1AC 468 #define H_DISABLE_AND_GETC 0x1B0 469 #define H_ERROR_DATA 0x1B4 470 #define H_GET_HCA_INFO 0x1B8 471 #define H_GET_PERF_COUNT 0x1BC 472 #define H_MANAGE_TRACE 0x1C0 473 #define H_GET_CPU_CHARACTERISTICS 0x1C8 474 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 475 #define H_QUERY_INT_STATE 0x1E4 476 #define H_POLL_PENDING 0x1D8 477 #define H_ILLAN_ATTRIBUTES 0x244 478 #define H_MODIFY_HEA_QP 0x250 479 #define H_QUERY_HEA_QP 0x254 480 #define H_QUERY_HEA 0x258 481 #define H_QUERY_HEA_PORT 0x25C 482 #define H_MODIFY_HEA_PORT 0x260 483 #define H_REG_BCMC 0x264 484 #define H_DEREG_BCMC 0x268 485 #define H_REGISTER_HEA_RPAGES 0x26C 486 #define H_DISABLE_AND_GET_HEA 0x270 487 #define H_GET_HEA_INFO 0x274 488 #define H_ALLOC_HEA_RESOURCE 0x278 489 #define H_ADD_CONN 0x284 490 #define H_DEL_CONN 0x288 491 #define H_JOIN 0x298 492 #define H_VASI_STATE 0x2A4 493 #define H_ENABLE_CRQ 0x2B0 494 #define H_GET_EM_PARMS 0x2B8 495 #define H_SET_MPP 0x2D0 496 #define H_GET_MPP 0x2D4 497 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 498 #define H_XIRR_X 0x2FC 499 #define H_RANDOM 0x300 500 #define H_SET_MODE 0x31C 501 #define H_RESIZE_HPT_PREPARE 0x36C 502 #define H_RESIZE_HPT_COMMIT 0x370 503 #define H_CLEAN_SLB 0x374 504 #define H_INVALIDATE_PID 0x378 505 #define H_REGISTER_PROC_TBL 0x37C 506 #define H_SIGNAL_SYS_RESET 0x380 507 508 #define H_INT_GET_SOURCE_INFO 0x3A8 509 #define H_INT_SET_SOURCE_CONFIG 0x3AC 510 #define H_INT_GET_SOURCE_CONFIG 0x3B0 511 #define H_INT_GET_QUEUE_INFO 0x3B4 512 #define H_INT_SET_QUEUE_CONFIG 0x3B8 513 #define H_INT_GET_QUEUE_CONFIG 0x3BC 514 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 515 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 516 #define H_INT_ESB 0x3C8 517 #define H_INT_SYNC 0x3CC 518 #define H_INT_RESET 0x3D0 519 #define H_SCM_READ_METADATA 0x3E4 520 #define H_SCM_WRITE_METADATA 0x3E8 521 #define H_SCM_BIND_MEM 0x3EC 522 #define H_SCM_UNBIND_MEM 0x3F0 523 #define H_SCM_UNBIND_ALL 0x3FC 524 525 #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL 526 527 /* The hcalls above are standardized in PAPR and implemented by pHyp 528 * as well. 529 * 530 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 531 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 532 * for "platform-specific" hcalls. 533 */ 534 #define KVMPPC_HCALL_BASE 0xf000 535 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 536 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 537 /* Client Architecture support */ 538 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 539 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 540 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 541 542 /* 543 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 544 * Secure VM mode via an Ultravisor / Protected Execution Facility 545 */ 546 #define SVM_HCALL_BASE 0xEF00 547 #define SVM_H_TPM_COMM 0xEF10 548 #define SVM_HCALL_MAX SVM_H_TPM_COMM 549 550 551 typedef struct SpaprDeviceTreeUpdateHeader { 552 uint32_t version_id; 553 } SpaprDeviceTreeUpdateHeader; 554 555 #define hcall_dprintf(fmt, ...) \ 556 do { \ 557 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 558 } while (0) 559 560 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 561 target_ulong opcode, 562 target_ulong *args); 563 564 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 565 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 566 target_ulong *args); 567 568 /* Virtual Processor Area structure constants */ 569 #define VPA_MIN_SIZE 640 570 #define VPA_SIZE_OFFSET 0x4 571 #define VPA_SHARED_PROC_OFFSET 0x9 572 #define VPA_SHARED_PROC_VAL 0x2 573 #define VPA_DISPATCH_COUNTER 0x100 574 575 /* ibm,set-eeh-option */ 576 #define RTAS_EEH_DISABLE 0 577 #define RTAS_EEH_ENABLE 1 578 #define RTAS_EEH_THAW_IO 2 579 #define RTAS_EEH_THAW_DMA 3 580 581 /* ibm,get-config-addr-info2 */ 582 #define RTAS_GET_PE_ADDR 0 583 #define RTAS_GET_PE_MODE 1 584 #define RTAS_PE_MODE_NONE 0 585 #define RTAS_PE_MODE_NOT_SHARED 1 586 #define RTAS_PE_MODE_SHARED 2 587 588 /* ibm,read-slot-reset-state2 */ 589 #define RTAS_EEH_PE_STATE_NORMAL 0 590 #define RTAS_EEH_PE_STATE_RESET 1 591 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 592 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 593 #define RTAS_EEH_PE_STATE_UNAVAIL 5 594 #define RTAS_EEH_NOT_SUPPORT 0 595 #define RTAS_EEH_SUPPORT 1 596 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 597 #define RTAS_EEH_PE_RECOVER_INFO 0 598 599 /* ibm,set-slot-reset */ 600 #define RTAS_SLOT_RESET_DEACTIVATE 0 601 #define RTAS_SLOT_RESET_HOT 1 602 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 603 604 /* ibm,slot-error-detail */ 605 #define RTAS_SLOT_TEMP_ERR_LOG 1 606 #define RTAS_SLOT_PERM_ERR_LOG 2 607 608 /* RTAS return codes */ 609 #define RTAS_OUT_SUCCESS 0 610 #define RTAS_OUT_NO_ERRORS_FOUND 1 611 #define RTAS_OUT_HW_ERROR -1 612 #define RTAS_OUT_BUSY -2 613 #define RTAS_OUT_PARAM_ERROR -3 614 #define RTAS_OUT_NOT_SUPPORTED -3 615 #define RTAS_OUT_NO_SUCH_INDICATOR -3 616 #define RTAS_OUT_NOT_AUTHORIZED -9002 617 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 618 619 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 620 #define RTAS_DDW_PGSIZE_4K 0x01 621 #define RTAS_DDW_PGSIZE_64K 0x02 622 #define RTAS_DDW_PGSIZE_16M 0x04 623 #define RTAS_DDW_PGSIZE_32M 0x08 624 #define RTAS_DDW_PGSIZE_64M 0x10 625 #define RTAS_DDW_PGSIZE_128M 0x20 626 #define RTAS_DDW_PGSIZE_256M 0x40 627 #define RTAS_DDW_PGSIZE_16G 0x80 628 629 /* RTAS tokens */ 630 #define RTAS_TOKEN_BASE 0x2000 631 632 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 633 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 634 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 635 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 636 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 637 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 638 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 639 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 640 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 641 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 642 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 643 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 644 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 645 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 646 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 647 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 648 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 649 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 650 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 651 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 652 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 653 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 654 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 655 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 656 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 657 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 658 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 659 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 660 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 661 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 662 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 663 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 664 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 665 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 666 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 667 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 668 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 669 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 670 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 671 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 672 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 673 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 674 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 675 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 676 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 677 678 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 679 680 /* RTAS ibm,get-system-parameter token values */ 681 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 682 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 683 #define RTAS_SYSPARM_UUID 48 684 685 /* RTAS indicator/sensor types 686 * 687 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 688 * 689 * NOTE: currently only DR-related sensors are implemented here 690 */ 691 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 692 #define RTAS_SENSOR_TYPE_DR 9002 693 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 694 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 695 696 /* Possible values for the platform-processor-diagnostics-run-mode parameter 697 * of the RTAS ibm,get-system-parameter call. 698 */ 699 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 700 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 701 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 702 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 703 704 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 705 { 706 return addr & ~0xF000000000000000ULL; 707 } 708 709 static inline uint32_t rtas_ld(target_ulong phys, int n) 710 { 711 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 712 } 713 714 static inline uint64_t rtas_ldq(target_ulong phys, int n) 715 { 716 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 717 } 718 719 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 720 { 721 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 722 } 723 724 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 725 uint32_t token, 726 uint32_t nargs, target_ulong args, 727 uint32_t nret, target_ulong rets); 728 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 729 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 730 uint32_t token, uint32_t nargs, target_ulong args, 731 uint32_t nret, target_ulong rets); 732 void spapr_dt_rtas_tokens(void *fdt, int rtas); 733 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 734 735 #define SPAPR_TCE_PAGE_SHIFT 12 736 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 737 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 738 739 #define SPAPR_VIO_BASE_LIOBN 0x00000000 740 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 741 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 742 (0x80000000 | ((phb_index) << 8) | (window_num)) 743 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 744 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 745 746 #define RTAS_SIZE 2048 747 #define RTAS_ERROR_LOG_MAX 2048 748 749 /* Offset from rtas-base where error log is placed */ 750 #define RTAS_ERROR_LOG_OFFSET 0x30 751 752 #define RTAS_EVENT_SCAN_RATE 1 753 754 /* This helper should be used to encode interrupt specifiers when the related 755 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 756 * VIO devices, RTAS event sources and PHBs). 757 */ 758 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 759 { 760 intspec[0] = cpu_to_be32(irq); 761 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 762 } 763 764 typedef struct SpaprTceTable SpaprTceTable; 765 766 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 767 #define SPAPR_TCE_TABLE(obj) \ 768 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 769 770 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 771 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 772 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 773 774 struct SpaprTceTable { 775 DeviceState parent; 776 uint32_t liobn; 777 uint32_t nb_table; 778 uint64_t bus_offset; 779 uint32_t page_shift; 780 uint64_t *table; 781 uint32_t mig_nb_table; 782 uint64_t *mig_table; 783 bool bypass; 784 bool need_vfio; 785 bool skipping_replay; 786 int fd; 787 MemoryRegion root; 788 IOMMUMemoryRegion iommu; 789 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 790 QLIST_ENTRY(SpaprTceTable) list; 791 }; 792 793 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 794 795 struct SpaprEventLogEntry { 796 uint32_t summary; 797 uint32_t extended_length; 798 void *extended_log; 799 QTAILQ_ENTRY(SpaprEventLogEntry) next; 800 }; 801 802 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 803 void spapr_events_init(SpaprMachineState *sm); 804 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 805 void close_htab_fd(SpaprMachineState *spapr); 806 void spapr_setup_hpt(SpaprMachineState *spapr); 807 void spapr_free_hpt(SpaprMachineState *spapr); 808 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 809 void spapr_tce_table_enable(SpaprTceTable *tcet, 810 uint32_t page_shift, uint64_t bus_offset, 811 uint32_t nb_table); 812 void spapr_tce_table_disable(SpaprTceTable *tcet); 813 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 814 815 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 816 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 817 uint32_t liobn, uint64_t window, uint32_t size); 818 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 819 SpaprTceTable *tcet); 820 void spapr_pci_switch_vga(bool big_endian); 821 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 822 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 823 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 824 uint32_t count); 825 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 826 uint32_t count); 827 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 828 uint32_t count, uint32_t index); 829 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 830 uint32_t count, uint32_t index); 831 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 832 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 833 Error **errp); 834 void spapr_clear_pending_events(SpaprMachineState *spapr); 835 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 836 int spapr_max_server_number(SpaprMachineState *spapr); 837 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 838 uint64_t pte0, uint64_t pte1); 839 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 840 841 /* DRC callbacks. */ 842 void spapr_core_release(DeviceState *dev); 843 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 844 void *fdt, int *fdt_start_offset, Error **errp); 845 void spapr_lmb_release(DeviceState *dev); 846 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 847 void *fdt, int *fdt_start_offset, Error **errp); 848 void spapr_phb_release(DeviceState *dev); 849 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 850 void *fdt, int *fdt_start_offset, Error **errp); 851 852 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 853 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 854 855 #define TYPE_SPAPR_RNG "spapr-rng" 856 857 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 858 859 /* 860 * This defines the maximum number of DIMM slots we can have for sPAPR 861 * guest. This is not defined by sPAPR but we are defining it to 32 slots 862 * based on default number of slots provided by PowerPC kernel. 863 */ 864 #define SPAPR_MAX_RAM_SLOTS 32 865 866 /* 1GB alignment for hotplug memory region */ 867 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 868 869 /* 870 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 871 * property under ibm,dynamic-reconfiguration-memory node. 872 */ 873 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 874 875 /* 876 * Defines for flag value in ibm,dynamic-memory property under 877 * ibm,dynamic-reconfiguration-memory node. 878 */ 879 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 880 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 881 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 882 883 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 884 885 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 886 887 int spapr_get_vcpu_id(PowerPCCPU *cpu); 888 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 889 PowerPCCPU *spapr_find_cpu(int vcpu_id); 890 891 int spapr_caps_pre_load(void *opaque); 892 int spapr_caps_pre_save(void *opaque); 893 894 /* 895 * Handling of optional capabilities 896 */ 897 extern const VMStateDescription vmstate_spapr_cap_htm; 898 extern const VMStateDescription vmstate_spapr_cap_vsx; 899 extern const VMStateDescription vmstate_spapr_cap_dfp; 900 extern const VMStateDescription vmstate_spapr_cap_cfpc; 901 extern const VMStateDescription vmstate_spapr_cap_sbbc; 902 extern const VMStateDescription vmstate_spapr_cap_ibs; 903 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 904 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 905 extern const VMStateDescription vmstate_spapr_cap_large_decr; 906 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 907 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 908 909 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 910 { 911 return spapr->eff.caps[cap]; 912 } 913 914 void spapr_caps_init(SpaprMachineState *spapr); 915 void spapr_caps_apply(SpaprMachineState *spapr); 916 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 917 void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp); 918 int spapr_caps_post_migration(SpaprMachineState *spapr); 919 920 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 921 Error **errp); 922 /* 923 * XIVE definitions 924 */ 925 #define SPAPR_OV5_XIVE_LEGACY 0x0 926 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 927 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 928 929 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 930 hwaddr spapr_get_rtas_addr(void); 931 #endif /* HW_SPAPR_H */ 932