1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 11 struct VIOsPAPRBus; 12 struct sPAPRPHBState; 13 struct sPAPRNVRAM; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 typedef struct sPAPREventSource sPAPREventSource; 16 typedef struct sPAPRPendingHPT sPAPRPendingHPT; 17 18 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 19 #define SPAPR_ENTRY_POINT 0x100 20 21 #define SPAPR_TIMEBASE_FREQ 512000000ULL 22 23 #define TYPE_SPAPR_RTC "spapr-rtc" 24 25 #define SPAPR_RTC(obj) \ 26 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 27 28 typedef struct sPAPRRTCState sPAPRRTCState; 29 struct sPAPRRTCState { 30 /*< private >*/ 31 DeviceState parent_obj; 32 int64_t ns_offset; 33 }; 34 35 typedef struct sPAPRDIMMState sPAPRDIMMState; 36 typedef struct sPAPRMachineClass sPAPRMachineClass; 37 38 #define TYPE_SPAPR_MACHINE "spapr-machine" 39 #define SPAPR_MACHINE(obj) \ 40 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 41 #define SPAPR_MACHINE_GET_CLASS(obj) \ 42 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 43 #define SPAPR_MACHINE_CLASS(klass) \ 44 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 45 46 typedef enum { 47 SPAPR_RESIZE_HPT_DEFAULT = 0, 48 SPAPR_RESIZE_HPT_DISABLED, 49 SPAPR_RESIZE_HPT_ENABLED, 50 SPAPR_RESIZE_HPT_REQUIRED, 51 } sPAPRResizeHPT; 52 53 /** 54 * Capabilities 55 */ 56 57 /* Hardware Transactional Memory */ 58 #define SPAPR_CAP_HTM 0x00 59 /* Vector Scalar Extensions */ 60 #define SPAPR_CAP_VSX 0x01 61 /* Decimal Floating Point */ 62 #define SPAPR_CAP_DFP 0x02 63 /* Num Caps */ 64 #define SPAPR_CAP_NUM (SPAPR_CAP_DFP + 1) 65 66 /* 67 * Capability Values 68 */ 69 /* Bool Caps */ 70 #define SPAPR_CAP_OFF 0x00 71 #define SPAPR_CAP_ON 0x01 72 /* Broken | Workaround | Fixed Caps */ 73 #define SPAPR_CAP_BROKEN 0x00 74 #define SPAPR_CAP_WORKAROUND 0x01 75 #define SPAPR_CAP_FIXED 0x02 76 77 typedef struct sPAPRCapabilities sPAPRCapabilities; 78 struct sPAPRCapabilities { 79 uint8_t caps[SPAPR_CAP_NUM]; 80 }; 81 82 /** 83 * sPAPRMachineClass: 84 */ 85 struct sPAPRMachineClass { 86 /*< private >*/ 87 MachineClass parent_class; 88 89 /*< public >*/ 90 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 91 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 92 bool pre_2_10_has_unused_icps; 93 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 94 uint64_t *buid, hwaddr *pio, 95 hwaddr *mmio32, hwaddr *mmio64, 96 unsigned n_dma, uint32_t *liobns, Error **errp); 97 sPAPRResizeHPT resize_hpt_default; 98 sPAPRCapabilities default_caps; 99 }; 100 101 /** 102 * sPAPRMachineState: 103 */ 104 struct sPAPRMachineState { 105 /*< private >*/ 106 MachineState parent_obj; 107 108 struct VIOsPAPRBus *vio_bus; 109 QLIST_HEAD(, sPAPRPHBState) phbs; 110 struct sPAPRNVRAM *nvram; 111 ICSState *ics; 112 sPAPRRTCState rtc; 113 114 sPAPRResizeHPT resize_hpt; 115 void *htab; 116 uint32_t htab_shift; 117 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 118 sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 119 120 hwaddr rma_size; 121 int vrma_adjust; 122 ssize_t rtas_size; 123 void *rtas_blob; 124 long kernel_size; 125 bool kernel_le; 126 uint32_t initrd_base; 127 long initrd_size; 128 uint64_t rtc_offset; /* Now used only during incoming migration */ 129 struct PPCTimebase tb; 130 bool has_graphics; 131 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 132 133 Notifier epow_notifier; 134 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 135 bool use_hotplug_event_source; 136 sPAPREventSource *event_sources; 137 138 /* ibm,client-architecture-support option negotiation */ 139 bool cas_reboot; 140 bool cas_legacy_guest_workaround; 141 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 142 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 143 uint32_t max_compat_pvr; 144 145 /* Migration state */ 146 int htab_save_index; 147 bool htab_first_pass; 148 int htab_fd; 149 150 /* Pending DIMM unplug cache. It is populated when a LMB 151 * unplug starts. It can be regenerated if a migration 152 * occurs during the unplug process. */ 153 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 154 155 /*< public >*/ 156 char *kvm_type; 157 MemoryHotplugState hotplug_memory; 158 159 const char *icp_type; 160 161 bool cmd_line_caps[SPAPR_CAP_NUM]; 162 sPAPRCapabilities def, eff, mig; 163 }; 164 165 #define H_SUCCESS 0 166 #define H_BUSY 1 /* Hardware busy -- retry later */ 167 #define H_CLOSED 2 /* Resource closed */ 168 #define H_NOT_AVAILABLE 3 169 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 170 #define H_PARTIAL 5 171 #define H_IN_PROGRESS 14 /* Kind of like busy */ 172 #define H_PAGE_REGISTERED 15 173 #define H_PARTIAL_STORE 16 174 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 175 #define H_CONTINUE 18 /* Returned from H_Join on success */ 176 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 177 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 178 is a good time to retry */ 179 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 180 is a good time to retry */ 181 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 182 is a good time to retry */ 183 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 184 is a good time to retry */ 185 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 186 is a good time to retry */ 187 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 188 is a good time to retry */ 189 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 190 #define H_HARDWARE -1 /* Hardware error */ 191 #define H_FUNCTION -2 /* Function not supported */ 192 #define H_PRIVILEGE -3 /* Caller not privileged */ 193 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 194 #define H_BAD_MODE -5 /* Illegal msr value */ 195 #define H_PTEG_FULL -6 /* PTEG is full */ 196 #define H_NOT_FOUND -7 /* PTE was not found" */ 197 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 198 #define H_NO_MEM -9 199 #define H_AUTHORITY -10 200 #define H_PERMISSION -11 201 #define H_DROPPED -12 202 #define H_SOURCE_PARM -13 203 #define H_DEST_PARM -14 204 #define H_REMOTE_PARM -15 205 #define H_RESOURCE -16 206 #define H_ADAPTER_PARM -17 207 #define H_RH_PARM -18 208 #define H_RCQ_PARM -19 209 #define H_SCQ_PARM -20 210 #define H_EQ_PARM -21 211 #define H_RT_PARM -22 212 #define H_ST_PARM -23 213 #define H_SIGT_PARM -24 214 #define H_TOKEN_PARM -25 215 #define H_MLENGTH_PARM -27 216 #define H_MEM_PARM -28 217 #define H_MEM_ACCESS_PARM -29 218 #define H_ATTR_PARM -30 219 #define H_PORT_PARM -31 220 #define H_MCG_PARM -32 221 #define H_VL_PARM -33 222 #define H_TSIZE_PARM -34 223 #define H_TRACE_PARM -35 224 225 #define H_MASK_PARM -37 226 #define H_MCG_FULL -38 227 #define H_ALIAS_EXIST -39 228 #define H_P_COUNTER -40 229 #define H_TABLE_FULL -41 230 #define H_ALT_TABLE -42 231 #define H_MR_CONDITION -43 232 #define H_NOT_ENOUGH_RESOURCES -44 233 #define H_R_STATE -45 234 #define H_RESCINDEND -46 235 #define H_P2 -55 236 #define H_P3 -56 237 #define H_P4 -57 238 #define H_P5 -58 239 #define H_P6 -59 240 #define H_P7 -60 241 #define H_P8 -61 242 #define H_P9 -62 243 #define H_UNSUPPORTED_FLAG -256 244 #define H_MULTI_THREADS_ACTIVE -9005 245 246 247 /* Long Busy is a condition that can be returned by the firmware 248 * when a call cannot be completed now, but the identical call 249 * should be retried later. This prevents calls blocking in the 250 * firmware for long periods of time. Annoyingly the firmware can return 251 * a range of return codes, hinting at how long we should wait before 252 * retrying. If you don't care for the hint, the macro below is a good 253 * way to check for the long_busy return codes 254 */ 255 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 256 && (x <= H_LONG_BUSY_END_RANGE)) 257 258 /* Flags */ 259 #define H_LARGE_PAGE (1ULL<<(63-16)) 260 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 261 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 262 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 263 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 264 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 265 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 266 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 267 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 268 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 269 #define H_ANDCOND (1ULL<<(63-33)) 270 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 271 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 272 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 273 #define H_COPY_PAGE (1ULL<<(63-49)) 274 #define H_N (1ULL<<(63-61)) 275 #define H_PP1 (1ULL<<(63-62)) 276 #define H_PP2 (1ULL<<(63-63)) 277 278 /* Values for 2nd argument to H_SET_MODE */ 279 #define H_SET_MODE_RESOURCE_SET_CIABR 1 280 #define H_SET_MODE_RESOURCE_SET_DAWR 2 281 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 282 #define H_SET_MODE_RESOURCE_LE 4 283 284 /* Flags for H_SET_MODE_RESOURCE_LE */ 285 #define H_SET_MODE_ENDIAN_BIG 0 286 #define H_SET_MODE_ENDIAN_LITTLE 1 287 288 /* VASI States */ 289 #define H_VASI_INVALID 0 290 #define H_VASI_ENABLED 1 291 #define H_VASI_ABORTED 2 292 #define H_VASI_SUSPENDING 3 293 #define H_VASI_SUSPENDED 4 294 #define H_VASI_RESUMED 5 295 #define H_VASI_COMPLETED 6 296 297 /* DABRX flags */ 298 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 299 #define H_DABRX_KERNEL (1ULL<<(63-62)) 300 #define H_DABRX_USER (1ULL<<(63-63)) 301 302 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 303 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 304 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 305 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 306 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 307 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 308 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 309 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 310 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 311 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 312 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 313 314 /* Each control block has to be on a 4K boundary */ 315 #define H_CB_ALIGNMENT 4096 316 317 /* pSeries hypervisor opcodes */ 318 #define H_REMOVE 0x04 319 #define H_ENTER 0x08 320 #define H_READ 0x0c 321 #define H_CLEAR_MOD 0x10 322 #define H_CLEAR_REF 0x14 323 #define H_PROTECT 0x18 324 #define H_GET_TCE 0x1c 325 #define H_PUT_TCE 0x20 326 #define H_SET_SPRG0 0x24 327 #define H_SET_DABR 0x28 328 #define H_PAGE_INIT 0x2c 329 #define H_SET_ASR 0x30 330 #define H_ASR_ON 0x34 331 #define H_ASR_OFF 0x38 332 #define H_LOGICAL_CI_LOAD 0x3c 333 #define H_LOGICAL_CI_STORE 0x40 334 #define H_LOGICAL_CACHE_LOAD 0x44 335 #define H_LOGICAL_CACHE_STORE 0x48 336 #define H_LOGICAL_ICBI 0x4c 337 #define H_LOGICAL_DCBF 0x50 338 #define H_GET_TERM_CHAR 0x54 339 #define H_PUT_TERM_CHAR 0x58 340 #define H_REAL_TO_LOGICAL 0x5c 341 #define H_HYPERVISOR_DATA 0x60 342 #define H_EOI 0x64 343 #define H_CPPR 0x68 344 #define H_IPI 0x6c 345 #define H_IPOLL 0x70 346 #define H_XIRR 0x74 347 #define H_PERFMON 0x7c 348 #define H_MIGRATE_DMA 0x78 349 #define H_REGISTER_VPA 0xDC 350 #define H_CEDE 0xE0 351 #define H_CONFER 0xE4 352 #define H_PROD 0xE8 353 #define H_GET_PPP 0xEC 354 #define H_SET_PPP 0xF0 355 #define H_PURR 0xF4 356 #define H_PIC 0xF8 357 #define H_REG_CRQ 0xFC 358 #define H_FREE_CRQ 0x100 359 #define H_VIO_SIGNAL 0x104 360 #define H_SEND_CRQ 0x108 361 #define H_COPY_RDMA 0x110 362 #define H_REGISTER_LOGICAL_LAN 0x114 363 #define H_FREE_LOGICAL_LAN 0x118 364 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 365 #define H_SEND_LOGICAL_LAN 0x120 366 #define H_BULK_REMOVE 0x124 367 #define H_MULTICAST_CTRL 0x130 368 #define H_SET_XDABR 0x134 369 #define H_STUFF_TCE 0x138 370 #define H_PUT_TCE_INDIRECT 0x13C 371 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 372 #define H_VTERM_PARTNER_INFO 0x150 373 #define H_REGISTER_VTERM 0x154 374 #define H_FREE_VTERM 0x158 375 #define H_RESET_EVENTS 0x15C 376 #define H_ALLOC_RESOURCE 0x160 377 #define H_FREE_RESOURCE 0x164 378 #define H_MODIFY_QP 0x168 379 #define H_QUERY_QP 0x16C 380 #define H_REREGISTER_PMR 0x170 381 #define H_REGISTER_SMR 0x174 382 #define H_QUERY_MR 0x178 383 #define H_QUERY_MW 0x17C 384 #define H_QUERY_HCA 0x180 385 #define H_QUERY_PORT 0x184 386 #define H_MODIFY_PORT 0x188 387 #define H_DEFINE_AQP1 0x18C 388 #define H_GET_TRACE_BUFFER 0x190 389 #define H_DEFINE_AQP0 0x194 390 #define H_RESIZE_MR 0x198 391 #define H_ATTACH_MCQP 0x19C 392 #define H_DETACH_MCQP 0x1A0 393 #define H_CREATE_RPT 0x1A4 394 #define H_REMOVE_RPT 0x1A8 395 #define H_REGISTER_RPAGES 0x1AC 396 #define H_DISABLE_AND_GETC 0x1B0 397 #define H_ERROR_DATA 0x1B4 398 #define H_GET_HCA_INFO 0x1B8 399 #define H_GET_PERF_COUNT 0x1BC 400 #define H_MANAGE_TRACE 0x1C0 401 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 402 #define H_QUERY_INT_STATE 0x1E4 403 #define H_POLL_PENDING 0x1D8 404 #define H_ILLAN_ATTRIBUTES 0x244 405 #define H_MODIFY_HEA_QP 0x250 406 #define H_QUERY_HEA_QP 0x254 407 #define H_QUERY_HEA 0x258 408 #define H_QUERY_HEA_PORT 0x25C 409 #define H_MODIFY_HEA_PORT 0x260 410 #define H_REG_BCMC 0x264 411 #define H_DEREG_BCMC 0x268 412 #define H_REGISTER_HEA_RPAGES 0x26C 413 #define H_DISABLE_AND_GET_HEA 0x270 414 #define H_GET_HEA_INFO 0x274 415 #define H_ALLOC_HEA_RESOURCE 0x278 416 #define H_ADD_CONN 0x284 417 #define H_DEL_CONN 0x288 418 #define H_JOIN 0x298 419 #define H_VASI_STATE 0x2A4 420 #define H_ENABLE_CRQ 0x2B0 421 #define H_GET_EM_PARMS 0x2B8 422 #define H_SET_MPP 0x2D0 423 #define H_GET_MPP 0x2D4 424 #define H_XIRR_X 0x2FC 425 #define H_RANDOM 0x300 426 #define H_SET_MODE 0x31C 427 #define H_RESIZE_HPT_PREPARE 0x36C 428 #define H_RESIZE_HPT_COMMIT 0x370 429 #define H_CLEAN_SLB 0x374 430 #define H_INVALIDATE_PID 0x378 431 #define H_REGISTER_PROC_TBL 0x37C 432 #define H_SIGNAL_SYS_RESET 0x380 433 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET 434 435 /* The hcalls above are standardized in PAPR and implemented by pHyp 436 * as well. 437 * 438 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 439 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 440 * for "platform-specific" hcalls. 441 */ 442 #define KVMPPC_HCALL_BASE 0xf000 443 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 444 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 445 /* Client Architecture support */ 446 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 447 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 448 449 typedef struct sPAPRDeviceTreeUpdateHeader { 450 uint32_t version_id; 451 } sPAPRDeviceTreeUpdateHeader; 452 453 #define hcall_dprintf(fmt, ...) \ 454 do { \ 455 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 456 } while (0) 457 458 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 459 target_ulong opcode, 460 target_ulong *args); 461 462 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 463 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 464 target_ulong *args); 465 466 /* ibm,set-eeh-option */ 467 #define RTAS_EEH_DISABLE 0 468 #define RTAS_EEH_ENABLE 1 469 #define RTAS_EEH_THAW_IO 2 470 #define RTAS_EEH_THAW_DMA 3 471 472 /* ibm,get-config-addr-info2 */ 473 #define RTAS_GET_PE_ADDR 0 474 #define RTAS_GET_PE_MODE 1 475 #define RTAS_PE_MODE_NONE 0 476 #define RTAS_PE_MODE_NOT_SHARED 1 477 #define RTAS_PE_MODE_SHARED 2 478 479 /* ibm,read-slot-reset-state2 */ 480 #define RTAS_EEH_PE_STATE_NORMAL 0 481 #define RTAS_EEH_PE_STATE_RESET 1 482 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 483 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 484 #define RTAS_EEH_PE_STATE_UNAVAIL 5 485 #define RTAS_EEH_NOT_SUPPORT 0 486 #define RTAS_EEH_SUPPORT 1 487 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 488 #define RTAS_EEH_PE_RECOVER_INFO 0 489 490 /* ibm,set-slot-reset */ 491 #define RTAS_SLOT_RESET_DEACTIVATE 0 492 #define RTAS_SLOT_RESET_HOT 1 493 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 494 495 /* ibm,slot-error-detail */ 496 #define RTAS_SLOT_TEMP_ERR_LOG 1 497 #define RTAS_SLOT_PERM_ERR_LOG 2 498 499 /* RTAS return codes */ 500 #define RTAS_OUT_SUCCESS 0 501 #define RTAS_OUT_NO_ERRORS_FOUND 1 502 #define RTAS_OUT_HW_ERROR -1 503 #define RTAS_OUT_BUSY -2 504 #define RTAS_OUT_PARAM_ERROR -3 505 #define RTAS_OUT_NOT_SUPPORTED -3 506 #define RTAS_OUT_NO_SUCH_INDICATOR -3 507 #define RTAS_OUT_NOT_AUTHORIZED -9002 508 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 509 510 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 511 #define RTAS_DDW_PGSIZE_4K 0x01 512 #define RTAS_DDW_PGSIZE_64K 0x02 513 #define RTAS_DDW_PGSIZE_16M 0x04 514 #define RTAS_DDW_PGSIZE_32M 0x08 515 #define RTAS_DDW_PGSIZE_64M 0x10 516 #define RTAS_DDW_PGSIZE_128M 0x20 517 #define RTAS_DDW_PGSIZE_256M 0x40 518 #define RTAS_DDW_PGSIZE_16G 0x80 519 520 /* RTAS tokens */ 521 #define RTAS_TOKEN_BASE 0x2000 522 523 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 524 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 525 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 526 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 527 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 528 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 529 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 530 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 531 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 532 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 533 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 534 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 535 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 536 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 537 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 538 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 539 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 540 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 541 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 542 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 543 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 544 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 545 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 546 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 547 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 548 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 549 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 550 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 551 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 552 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 553 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 554 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 555 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 556 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 557 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 558 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 559 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 560 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 561 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 562 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 563 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 564 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 565 566 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 567 568 /* RTAS ibm,get-system-parameter token values */ 569 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 570 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 571 #define RTAS_SYSPARM_UUID 48 572 573 /* RTAS indicator/sensor types 574 * 575 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 576 * 577 * NOTE: currently only DR-related sensors are implemented here 578 */ 579 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 580 #define RTAS_SENSOR_TYPE_DR 9002 581 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 582 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 583 584 /* Possible values for the platform-processor-diagnostics-run-mode parameter 585 * of the RTAS ibm,get-system-parameter call. 586 */ 587 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 588 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 589 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 590 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 591 592 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 593 { 594 return addr & ~0xF000000000000000ULL; 595 } 596 597 static inline uint32_t rtas_ld(target_ulong phys, int n) 598 { 599 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 600 } 601 602 static inline uint64_t rtas_ldq(target_ulong phys, int n) 603 { 604 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 605 } 606 607 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 608 { 609 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 610 } 611 612 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 613 uint32_t token, 614 uint32_t nargs, target_ulong args, 615 uint32_t nret, target_ulong rets); 616 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 617 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 618 uint32_t token, uint32_t nargs, target_ulong args, 619 uint32_t nret, target_ulong rets); 620 void spapr_dt_rtas_tokens(void *fdt, int rtas); 621 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 622 623 #define SPAPR_TCE_PAGE_SHIFT 12 624 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 625 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 626 627 #define SPAPR_VIO_BASE_LIOBN 0x00000000 628 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 629 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 630 (0x80000000 | ((phb_index) << 8) | (window_num)) 631 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 632 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 633 634 #define RTAS_ERROR_LOG_MAX 2048 635 636 #define RTAS_EVENT_SCAN_RATE 1 637 638 /* This helper should be used to encode interrupt specifiers when the related 639 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 640 * VIO devices, RTAS event sources and PHBs). 641 */ 642 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi) 643 { 644 intspec[0] = cpu_to_be32(irq); 645 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 646 } 647 648 typedef struct sPAPRTCETable sPAPRTCETable; 649 650 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 651 #define SPAPR_TCE_TABLE(obj) \ 652 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 653 654 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 655 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 656 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 657 658 struct sPAPRTCETable { 659 DeviceState parent; 660 uint32_t liobn; 661 uint32_t nb_table; 662 uint64_t bus_offset; 663 uint32_t page_shift; 664 uint64_t *table; 665 uint32_t mig_nb_table; 666 uint64_t *mig_table; 667 bool bypass; 668 bool need_vfio; 669 int fd; 670 MemoryRegion root; 671 IOMMUMemoryRegion iommu; 672 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 673 QLIST_ENTRY(sPAPRTCETable) list; 674 }; 675 676 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 677 678 struct sPAPREventLogEntry { 679 uint32_t summary; 680 uint32_t extended_length; 681 void *extended_log; 682 QTAILQ_ENTRY(sPAPREventLogEntry) next; 683 }; 684 685 void spapr_events_init(sPAPRMachineState *sm); 686 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 687 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 688 target_ulong addr, target_ulong size, 689 sPAPROptionVector *ov5_updates); 690 void close_htab_fd(sPAPRMachineState *spapr); 691 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 692 void spapr_free_hpt(sPAPRMachineState *spapr); 693 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 694 void spapr_tce_table_enable(sPAPRTCETable *tcet, 695 uint32_t page_shift, uint64_t bus_offset, 696 uint32_t nb_table); 697 void spapr_tce_table_disable(sPAPRTCETable *tcet); 698 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 699 700 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 701 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 702 uint32_t liobn, uint64_t window, uint32_t size); 703 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 704 sPAPRTCETable *tcet); 705 void spapr_pci_switch_vga(bool big_endian); 706 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 707 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 708 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 709 uint32_t count); 710 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 711 uint32_t count); 712 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 713 uint32_t count, uint32_t index); 714 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 715 uint32_t count, uint32_t index); 716 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 717 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 718 Error **errp); 719 void spapr_clear_pending_events(sPAPRMachineState *spapr); 720 721 /* CPU and LMB DRC release callbacks. */ 722 void spapr_core_release(DeviceState *dev); 723 void spapr_lmb_release(DeviceState *dev); 724 725 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 726 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 727 728 #define TYPE_SPAPR_RNG "spapr-rng" 729 730 int spapr_rng_populate_dt(void *fdt); 731 732 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 733 734 /* 735 * This defines the maximum number of DIMM slots we can have for sPAPR 736 * guest. This is not defined by sPAPR but we are defining it to 32 slots 737 * based on default number of slots provided by PowerPC kernel. 738 */ 739 #define SPAPR_MAX_RAM_SLOTS 32 740 741 /* 1GB alignment for hotplug memory region */ 742 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 743 744 /* 745 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 746 * property under ibm,dynamic-reconfiguration-memory node. 747 */ 748 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 749 750 /* 751 * Defines for flag value in ibm,dynamic-memory property under 752 * ibm,dynamic-reconfiguration-memory node. 753 */ 754 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 755 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 756 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 757 758 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 759 760 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 761 762 int spapr_vcpu_id(PowerPCCPU *cpu); 763 PowerPCCPU *spapr_find_cpu(int vcpu_id); 764 765 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 766 Error **errp); 767 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 768 bool align, Error **errp); 769 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); 770 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); 771 772 773 int spapr_caps_pre_load(void *opaque); 774 int spapr_caps_pre_save(void *opaque); 775 776 /* 777 * Handling of optional capabilities 778 */ 779 extern const VMStateDescription vmstate_spapr_cap_htm; 780 extern const VMStateDescription vmstate_spapr_cap_vsx; 781 extern const VMStateDescription vmstate_spapr_cap_dfp; 782 783 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap) 784 { 785 return spapr->eff.caps[cap]; 786 } 787 788 void spapr_caps_reset(sPAPRMachineState *spapr); 789 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); 790 int spapr_caps_post_migration(sPAPRMachineState *spapr); 791 792 #endif /* HW_SPAPR_H */ 793