1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 10 struct VIOsPAPRBus; 11 struct sPAPRPHBState; 12 struct sPAPRNVRAM; 13 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 16 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 17 #define SPAPR_ENTRY_POINT 0x100 18 19 #define SPAPR_TIMEBASE_FREQ 512000000ULL 20 21 typedef struct sPAPRMachineClass sPAPRMachineClass; 22 typedef struct sPAPRMachineState sPAPRMachineState; 23 24 #define TYPE_SPAPR_MACHINE "spapr-machine" 25 #define SPAPR_MACHINE(obj) \ 26 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 27 #define SPAPR_MACHINE_GET_CLASS(obj) \ 28 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 29 #define SPAPR_MACHINE_CLASS(klass) \ 30 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 31 32 /** 33 * sPAPRMachineClass: 34 */ 35 struct sPAPRMachineClass { 36 /*< private >*/ 37 MachineClass parent_class; 38 39 /*< public >*/ 40 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 41 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 42 const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */ 43 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 44 uint64_t *buid, hwaddr *pio, hwaddr *mmio, 45 unsigned n_dma, uint32_t *liobns, Error **errp); 46 }; 47 48 /** 49 * sPAPRMachineState: 50 */ 51 struct sPAPRMachineState { 52 /*< private >*/ 53 MachineState parent_obj; 54 55 struct VIOsPAPRBus *vio_bus; 56 QLIST_HEAD(, sPAPRPHBState) phbs; 57 struct sPAPRNVRAM *nvram; 58 XICSState *xics; 59 DeviceState *rtc; 60 61 void *htab; 62 uint32_t htab_shift; 63 hwaddr rma_size; 64 int vrma_adjust; 65 hwaddr fdt_addr, rtas_addr; 66 ssize_t rtas_size; 67 void *rtas_blob; 68 void *fdt_skel; 69 uint64_t rtc_offset; /* Now used only during incoming migration */ 70 struct PPCTimebase tb; 71 bool has_graphics; 72 73 uint32_t check_exception_irq; 74 Notifier epow_notifier; 75 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 76 77 /* Migration state */ 78 int htab_save_index; 79 bool htab_first_pass; 80 int htab_fd; 81 82 /* RTAS state */ 83 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list; 84 85 /*< public >*/ 86 char *kvm_type; 87 MemoryHotplugState hotplug_memory; 88 Object **cores; 89 }; 90 91 #define H_SUCCESS 0 92 #define H_BUSY 1 /* Hardware busy -- retry later */ 93 #define H_CLOSED 2 /* Resource closed */ 94 #define H_NOT_AVAILABLE 3 95 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 96 #define H_PARTIAL 5 97 #define H_IN_PROGRESS 14 /* Kind of like busy */ 98 #define H_PAGE_REGISTERED 15 99 #define H_PARTIAL_STORE 16 100 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 101 #define H_CONTINUE 18 /* Returned from H_Join on success */ 102 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 103 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 104 is a good time to retry */ 105 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 106 is a good time to retry */ 107 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 108 is a good time to retry */ 109 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 110 is a good time to retry */ 111 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 112 is a good time to retry */ 113 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 114 is a good time to retry */ 115 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 116 #define H_HARDWARE -1 /* Hardware error */ 117 #define H_FUNCTION -2 /* Function not supported */ 118 #define H_PRIVILEGE -3 /* Caller not privileged */ 119 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 120 #define H_BAD_MODE -5 /* Illegal msr value */ 121 #define H_PTEG_FULL -6 /* PTEG is full */ 122 #define H_NOT_FOUND -7 /* PTE was not found" */ 123 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 124 #define H_NO_MEM -9 125 #define H_AUTHORITY -10 126 #define H_PERMISSION -11 127 #define H_DROPPED -12 128 #define H_SOURCE_PARM -13 129 #define H_DEST_PARM -14 130 #define H_REMOTE_PARM -15 131 #define H_RESOURCE -16 132 #define H_ADAPTER_PARM -17 133 #define H_RH_PARM -18 134 #define H_RCQ_PARM -19 135 #define H_SCQ_PARM -20 136 #define H_EQ_PARM -21 137 #define H_RT_PARM -22 138 #define H_ST_PARM -23 139 #define H_SIGT_PARM -24 140 #define H_TOKEN_PARM -25 141 #define H_MLENGTH_PARM -27 142 #define H_MEM_PARM -28 143 #define H_MEM_ACCESS_PARM -29 144 #define H_ATTR_PARM -30 145 #define H_PORT_PARM -31 146 #define H_MCG_PARM -32 147 #define H_VL_PARM -33 148 #define H_TSIZE_PARM -34 149 #define H_TRACE_PARM -35 150 151 #define H_MASK_PARM -37 152 #define H_MCG_FULL -38 153 #define H_ALIAS_EXIST -39 154 #define H_P_COUNTER -40 155 #define H_TABLE_FULL -41 156 #define H_ALT_TABLE -42 157 #define H_MR_CONDITION -43 158 #define H_NOT_ENOUGH_RESOURCES -44 159 #define H_R_STATE -45 160 #define H_RESCINDEND -46 161 #define H_P2 -55 162 #define H_P3 -56 163 #define H_P4 -57 164 #define H_P5 -58 165 #define H_P6 -59 166 #define H_P7 -60 167 #define H_P8 -61 168 #define H_P9 -62 169 #define H_UNSUPPORTED_FLAG -256 170 #define H_MULTI_THREADS_ACTIVE -9005 171 172 173 /* Long Busy is a condition that can be returned by the firmware 174 * when a call cannot be completed now, but the identical call 175 * should be retried later. This prevents calls blocking in the 176 * firmware for long periods of time. Annoyingly the firmware can return 177 * a range of return codes, hinting at how long we should wait before 178 * retrying. If you don't care for the hint, the macro below is a good 179 * way to check for the long_busy return codes 180 */ 181 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 182 && (x <= H_LONG_BUSY_END_RANGE)) 183 184 /* Flags */ 185 #define H_LARGE_PAGE (1ULL<<(63-16)) 186 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 187 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 188 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 189 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 190 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 191 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 192 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 193 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 194 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 195 #define H_ANDCOND (1ULL<<(63-33)) 196 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 197 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 198 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 199 #define H_COPY_PAGE (1ULL<<(63-49)) 200 #define H_N (1ULL<<(63-61)) 201 #define H_PP1 (1ULL<<(63-62)) 202 #define H_PP2 (1ULL<<(63-63)) 203 204 /* Values for 2nd argument to H_SET_MODE */ 205 #define H_SET_MODE_RESOURCE_SET_CIABR 1 206 #define H_SET_MODE_RESOURCE_SET_DAWR 2 207 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 208 #define H_SET_MODE_RESOURCE_LE 4 209 210 /* Flags for H_SET_MODE_RESOURCE_LE */ 211 #define H_SET_MODE_ENDIAN_BIG 0 212 #define H_SET_MODE_ENDIAN_LITTLE 1 213 214 /* VASI States */ 215 #define H_VASI_INVALID 0 216 #define H_VASI_ENABLED 1 217 #define H_VASI_ABORTED 2 218 #define H_VASI_SUSPENDING 3 219 #define H_VASI_SUSPENDED 4 220 #define H_VASI_RESUMED 5 221 #define H_VASI_COMPLETED 6 222 223 /* DABRX flags */ 224 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 225 #define H_DABRX_KERNEL (1ULL<<(63-62)) 226 #define H_DABRX_USER (1ULL<<(63-63)) 227 228 /* Each control block has to be on a 4K boundary */ 229 #define H_CB_ALIGNMENT 4096 230 231 /* pSeries hypervisor opcodes */ 232 #define H_REMOVE 0x04 233 #define H_ENTER 0x08 234 #define H_READ 0x0c 235 #define H_CLEAR_MOD 0x10 236 #define H_CLEAR_REF 0x14 237 #define H_PROTECT 0x18 238 #define H_GET_TCE 0x1c 239 #define H_PUT_TCE 0x20 240 #define H_SET_SPRG0 0x24 241 #define H_SET_DABR 0x28 242 #define H_PAGE_INIT 0x2c 243 #define H_SET_ASR 0x30 244 #define H_ASR_ON 0x34 245 #define H_ASR_OFF 0x38 246 #define H_LOGICAL_CI_LOAD 0x3c 247 #define H_LOGICAL_CI_STORE 0x40 248 #define H_LOGICAL_CACHE_LOAD 0x44 249 #define H_LOGICAL_CACHE_STORE 0x48 250 #define H_LOGICAL_ICBI 0x4c 251 #define H_LOGICAL_DCBF 0x50 252 #define H_GET_TERM_CHAR 0x54 253 #define H_PUT_TERM_CHAR 0x58 254 #define H_REAL_TO_LOGICAL 0x5c 255 #define H_HYPERVISOR_DATA 0x60 256 #define H_EOI 0x64 257 #define H_CPPR 0x68 258 #define H_IPI 0x6c 259 #define H_IPOLL 0x70 260 #define H_XIRR 0x74 261 #define H_PERFMON 0x7c 262 #define H_MIGRATE_DMA 0x78 263 #define H_REGISTER_VPA 0xDC 264 #define H_CEDE 0xE0 265 #define H_CONFER 0xE4 266 #define H_PROD 0xE8 267 #define H_GET_PPP 0xEC 268 #define H_SET_PPP 0xF0 269 #define H_PURR 0xF4 270 #define H_PIC 0xF8 271 #define H_REG_CRQ 0xFC 272 #define H_FREE_CRQ 0x100 273 #define H_VIO_SIGNAL 0x104 274 #define H_SEND_CRQ 0x108 275 #define H_COPY_RDMA 0x110 276 #define H_REGISTER_LOGICAL_LAN 0x114 277 #define H_FREE_LOGICAL_LAN 0x118 278 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 279 #define H_SEND_LOGICAL_LAN 0x120 280 #define H_BULK_REMOVE 0x124 281 #define H_MULTICAST_CTRL 0x130 282 #define H_SET_XDABR 0x134 283 #define H_STUFF_TCE 0x138 284 #define H_PUT_TCE_INDIRECT 0x13C 285 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 286 #define H_VTERM_PARTNER_INFO 0x150 287 #define H_REGISTER_VTERM 0x154 288 #define H_FREE_VTERM 0x158 289 #define H_RESET_EVENTS 0x15C 290 #define H_ALLOC_RESOURCE 0x160 291 #define H_FREE_RESOURCE 0x164 292 #define H_MODIFY_QP 0x168 293 #define H_QUERY_QP 0x16C 294 #define H_REREGISTER_PMR 0x170 295 #define H_REGISTER_SMR 0x174 296 #define H_QUERY_MR 0x178 297 #define H_QUERY_MW 0x17C 298 #define H_QUERY_HCA 0x180 299 #define H_QUERY_PORT 0x184 300 #define H_MODIFY_PORT 0x188 301 #define H_DEFINE_AQP1 0x18C 302 #define H_GET_TRACE_BUFFER 0x190 303 #define H_DEFINE_AQP0 0x194 304 #define H_RESIZE_MR 0x198 305 #define H_ATTACH_MCQP 0x19C 306 #define H_DETACH_MCQP 0x1A0 307 #define H_CREATE_RPT 0x1A4 308 #define H_REMOVE_RPT 0x1A8 309 #define H_REGISTER_RPAGES 0x1AC 310 #define H_DISABLE_AND_GETC 0x1B0 311 #define H_ERROR_DATA 0x1B4 312 #define H_GET_HCA_INFO 0x1B8 313 #define H_GET_PERF_COUNT 0x1BC 314 #define H_MANAGE_TRACE 0x1C0 315 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 316 #define H_QUERY_INT_STATE 0x1E4 317 #define H_POLL_PENDING 0x1D8 318 #define H_ILLAN_ATTRIBUTES 0x244 319 #define H_MODIFY_HEA_QP 0x250 320 #define H_QUERY_HEA_QP 0x254 321 #define H_QUERY_HEA 0x258 322 #define H_QUERY_HEA_PORT 0x25C 323 #define H_MODIFY_HEA_PORT 0x260 324 #define H_REG_BCMC 0x264 325 #define H_DEREG_BCMC 0x268 326 #define H_REGISTER_HEA_RPAGES 0x26C 327 #define H_DISABLE_AND_GET_HEA 0x270 328 #define H_GET_HEA_INFO 0x274 329 #define H_ALLOC_HEA_RESOURCE 0x278 330 #define H_ADD_CONN 0x284 331 #define H_DEL_CONN 0x288 332 #define H_JOIN 0x298 333 #define H_VASI_STATE 0x2A4 334 #define H_ENABLE_CRQ 0x2B0 335 #define H_GET_EM_PARMS 0x2B8 336 #define H_SET_MPP 0x2D0 337 #define H_GET_MPP 0x2D4 338 #define H_XIRR_X 0x2FC 339 #define H_RANDOM 0x300 340 #define H_SET_MODE 0x31C 341 #define MAX_HCALL_OPCODE H_SET_MODE 342 343 /* The hcalls above are standardized in PAPR and implemented by pHyp 344 * as well. 345 * 346 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 347 * So far we just need one for H_RTAS, but in future we'll need more 348 * for extensions like virtio. We put those into the 0xf000-0xfffc 349 * range which is reserved by PAPR for "platform-specific" hcalls. 350 */ 351 #define KVMPPC_HCALL_BASE 0xf000 352 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 353 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 354 /* Client Architecture support */ 355 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 356 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 357 358 typedef struct sPAPRDeviceTreeUpdateHeader { 359 uint32_t version_id; 360 } sPAPRDeviceTreeUpdateHeader; 361 362 #define hcall_dprintf(fmt, ...) \ 363 do { \ 364 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 365 } while (0) 366 367 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 368 target_ulong opcode, 369 target_ulong *args); 370 371 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 372 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 373 target_ulong *args); 374 375 /* ibm,set-eeh-option */ 376 #define RTAS_EEH_DISABLE 0 377 #define RTAS_EEH_ENABLE 1 378 #define RTAS_EEH_THAW_IO 2 379 #define RTAS_EEH_THAW_DMA 3 380 381 /* ibm,get-config-addr-info2 */ 382 #define RTAS_GET_PE_ADDR 0 383 #define RTAS_GET_PE_MODE 1 384 #define RTAS_PE_MODE_NONE 0 385 #define RTAS_PE_MODE_NOT_SHARED 1 386 #define RTAS_PE_MODE_SHARED 2 387 388 /* ibm,read-slot-reset-state2 */ 389 #define RTAS_EEH_PE_STATE_NORMAL 0 390 #define RTAS_EEH_PE_STATE_RESET 1 391 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 392 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 393 #define RTAS_EEH_PE_STATE_UNAVAIL 5 394 #define RTAS_EEH_NOT_SUPPORT 0 395 #define RTAS_EEH_SUPPORT 1 396 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 397 #define RTAS_EEH_PE_RECOVER_INFO 0 398 399 /* ibm,set-slot-reset */ 400 #define RTAS_SLOT_RESET_DEACTIVATE 0 401 #define RTAS_SLOT_RESET_HOT 1 402 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 403 404 /* ibm,slot-error-detail */ 405 #define RTAS_SLOT_TEMP_ERR_LOG 1 406 #define RTAS_SLOT_PERM_ERR_LOG 2 407 408 /* RTAS return codes */ 409 #define RTAS_OUT_SUCCESS 0 410 #define RTAS_OUT_NO_ERRORS_FOUND 1 411 #define RTAS_OUT_HW_ERROR -1 412 #define RTAS_OUT_BUSY -2 413 #define RTAS_OUT_PARAM_ERROR -3 414 #define RTAS_OUT_NOT_SUPPORTED -3 415 #define RTAS_OUT_NO_SUCH_INDICATOR -3 416 #define RTAS_OUT_NOT_AUTHORIZED -9002 417 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 418 419 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 420 #define RTAS_DDW_PGSIZE_4K 0x01 421 #define RTAS_DDW_PGSIZE_64K 0x02 422 #define RTAS_DDW_PGSIZE_16M 0x04 423 #define RTAS_DDW_PGSIZE_32M 0x08 424 #define RTAS_DDW_PGSIZE_64M 0x10 425 #define RTAS_DDW_PGSIZE_128M 0x20 426 #define RTAS_DDW_PGSIZE_256M 0x40 427 #define RTAS_DDW_PGSIZE_16G 0x80 428 429 /* RTAS tokens */ 430 #define RTAS_TOKEN_BASE 0x2000 431 432 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 433 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 434 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 435 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 436 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 437 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 438 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 439 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 440 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 441 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 442 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 443 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 444 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 445 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 446 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 447 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 448 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 449 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 450 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 451 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 452 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 453 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 454 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 455 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 456 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 457 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 458 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 459 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 460 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 461 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 462 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 463 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 464 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 465 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 466 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 467 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 468 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 469 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 470 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 471 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 472 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 473 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 474 475 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 476 477 /* RTAS ibm,get-system-parameter token values */ 478 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 479 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 480 #define RTAS_SYSPARM_UUID 48 481 482 /* RTAS indicator/sensor types 483 * 484 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 485 * 486 * NOTE: currently only DR-related sensors are implemented here 487 */ 488 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 489 #define RTAS_SENSOR_TYPE_DR 9002 490 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 491 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 492 493 /* Possible values for the platform-processor-diagnostics-run-mode parameter 494 * of the RTAS ibm,get-system-parameter call. 495 */ 496 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 497 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 498 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 499 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 500 501 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 502 { 503 return addr & ~0xF000000000000000ULL; 504 } 505 506 static inline uint32_t rtas_ld(target_ulong phys, int n) 507 { 508 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 509 } 510 511 static inline uint64_t rtas_ldq(target_ulong phys, int n) 512 { 513 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 514 } 515 516 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 517 { 518 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 519 } 520 521 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 522 uint32_t token, 523 uint32_t nargs, target_ulong args, 524 uint32_t nret, target_ulong rets); 525 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 526 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 527 uint32_t token, uint32_t nargs, target_ulong args, 528 uint32_t nret, target_ulong rets); 529 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 530 hwaddr rtas_size); 531 532 #define SPAPR_TCE_PAGE_SHIFT 12 533 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 534 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 535 536 #define SPAPR_VIO_BASE_LIOBN 0x00000000 537 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 538 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 539 (0x80000000 | ((phb_index) << 8) | (window_num)) 540 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 541 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 542 543 #define RTAS_ERROR_LOG_MAX 2048 544 545 #define RTAS_EVENT_SCAN_RATE 1 546 547 typedef struct sPAPRTCETable sPAPRTCETable; 548 549 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 550 #define SPAPR_TCE_TABLE(obj) \ 551 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 552 553 struct sPAPRTCETable { 554 DeviceState parent; 555 uint32_t liobn; 556 uint32_t nb_table; 557 uint64_t bus_offset; 558 uint32_t page_shift; 559 uint64_t *table; 560 uint32_t mig_nb_table; 561 uint64_t *mig_table; 562 bool bypass; 563 bool need_vfio; 564 int fd; 565 MemoryRegion root, iommu; 566 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 567 QLIST_ENTRY(sPAPRTCETable) list; 568 }; 569 570 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 571 572 struct sPAPREventLogEntry { 573 int log_type; 574 bool exception; 575 void *data; 576 QTAILQ_ENTRY(sPAPREventLogEntry) next; 577 }; 578 579 void spapr_events_init(sPAPRMachineState *sm); 580 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 581 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 582 target_ulong addr, target_ulong size, 583 bool cpu_update, bool memory_update); 584 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 585 void spapr_tce_table_enable(sPAPRTCETable *tcet, 586 uint32_t page_shift, uint64_t bus_offset, 587 uint32_t nb_table); 588 void spapr_tce_table_disable(sPAPRTCETable *tcet); 589 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 590 591 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 592 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 593 uint32_t liobn, uint64_t window, uint32_t size); 594 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 595 sPAPRTCETable *tcet); 596 void spapr_pci_switch_vga(bool big_endian); 597 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 598 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 599 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 600 uint32_t count); 601 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 602 uint32_t count); 603 void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp); 604 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 605 sPAPRMachineState *spapr); 606 607 /* rtas-configure-connector state */ 608 struct sPAPRConfigureConnectorState { 609 uint32_t drc_index; 610 int fdt_offset; 611 int fdt_depth; 612 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next; 613 }; 614 615 void spapr_ccs_reset_hook(void *opaque); 616 617 #define TYPE_SPAPR_RTC "spapr-rtc" 618 #define TYPE_SPAPR_RNG "spapr-rng" 619 620 void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); 621 int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); 622 623 int spapr_rng_populate_dt(void *fdt); 624 625 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 626 627 /* 628 * This defines the maximum number of DIMM slots we can have for sPAPR 629 * guest. This is not defined by sPAPR but we are defining it to 32 slots 630 * based on default number of slots provided by PowerPC kernel. 631 */ 632 #define SPAPR_MAX_RAM_SLOTS 32 633 634 /* 1GB alignment for hotplug memory region */ 635 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 636 637 /* 638 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 639 * property under ibm,dynamic-reconfiguration-memory node. 640 */ 641 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 642 643 /* 644 * Defines for flag value in ibm,dynamic-memory property under 645 * ibm,dynamic-reconfiguration-memory node. 646 */ 647 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 648 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 649 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 650 651 #endif /* HW_SPAPR_H */ 652