1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 11 struct VIOsPAPRBus; 12 struct sPAPRPHBState; 13 struct sPAPRNVRAM; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 typedef struct sPAPREventSource sPAPREventSource; 16 typedef struct sPAPRPendingHPT sPAPRPendingHPT; 17 18 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 19 #define SPAPR_ENTRY_POINT 0x100 20 21 #define SPAPR_TIMEBASE_FREQ 512000000ULL 22 23 #define TYPE_SPAPR_RTC "spapr-rtc" 24 25 #define SPAPR_RTC(obj) \ 26 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 27 28 typedef struct sPAPRRTCState sPAPRRTCState; 29 struct sPAPRRTCState { 30 /*< private >*/ 31 DeviceState parent_obj; 32 int64_t ns_offset; 33 }; 34 35 typedef struct sPAPRDIMMState sPAPRDIMMState; 36 typedef struct sPAPRMachineClass sPAPRMachineClass; 37 38 #define TYPE_SPAPR_MACHINE "spapr-machine" 39 #define SPAPR_MACHINE(obj) \ 40 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 41 #define SPAPR_MACHINE_GET_CLASS(obj) \ 42 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 43 #define SPAPR_MACHINE_CLASS(klass) \ 44 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 45 46 typedef enum { 47 SPAPR_RESIZE_HPT_DEFAULT = 0, 48 SPAPR_RESIZE_HPT_DISABLED, 49 SPAPR_RESIZE_HPT_ENABLED, 50 SPAPR_RESIZE_HPT_REQUIRED, 51 } sPAPRResizeHPT; 52 53 /** 54 * Capabilities 55 */ 56 57 typedef struct sPAPRCapabilities sPAPRCapabilities; 58 struct sPAPRCapabilities { 59 uint64_t mask; 60 }; 61 62 /** 63 * sPAPRMachineClass: 64 */ 65 struct sPAPRMachineClass { 66 /*< private >*/ 67 MachineClass parent_class; 68 69 /*< public >*/ 70 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 71 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 72 bool pre_2_10_has_unused_icps; 73 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 74 uint64_t *buid, hwaddr *pio, 75 hwaddr *mmio32, hwaddr *mmio64, 76 unsigned n_dma, uint32_t *liobns, Error **errp); 77 sPAPRResizeHPT resize_hpt_default; 78 sPAPRCapabilities default_caps; 79 }; 80 81 /** 82 * sPAPRMachineState: 83 */ 84 struct sPAPRMachineState { 85 /*< private >*/ 86 MachineState parent_obj; 87 88 struct VIOsPAPRBus *vio_bus; 89 QLIST_HEAD(, sPAPRPHBState) phbs; 90 struct sPAPRNVRAM *nvram; 91 ICSState *ics; 92 sPAPRRTCState rtc; 93 94 sPAPRResizeHPT resize_hpt; 95 void *htab; 96 uint32_t htab_shift; 97 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 98 sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 99 100 hwaddr rma_size; 101 int vrma_adjust; 102 ssize_t rtas_size; 103 void *rtas_blob; 104 long kernel_size; 105 bool kernel_le; 106 uint32_t initrd_base; 107 long initrd_size; 108 uint64_t rtc_offset; /* Now used only during incoming migration */ 109 struct PPCTimebase tb; 110 bool has_graphics; 111 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 112 113 Notifier epow_notifier; 114 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 115 bool use_hotplug_event_source; 116 sPAPREventSource *event_sources; 117 118 /* ibm,client-architecture-support option negotiation */ 119 bool cas_reboot; 120 bool cas_legacy_guest_workaround; 121 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 122 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 123 uint32_t max_compat_pvr; 124 125 /* Migration state */ 126 int htab_save_index; 127 bool htab_first_pass; 128 int htab_fd; 129 130 /* Pending DIMM unplug cache. It is populated when a LMB 131 * unplug starts. It can be regenerated if a migration 132 * occurs during the unplug process. */ 133 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 134 135 /*< public >*/ 136 char *kvm_type; 137 MemoryHotplugState hotplug_memory; 138 139 const char *icp_type; 140 141 sPAPRCapabilities forced_caps, forbidden_caps; 142 sPAPRCapabilities effective_caps; 143 }; 144 145 #define H_SUCCESS 0 146 #define H_BUSY 1 /* Hardware busy -- retry later */ 147 #define H_CLOSED 2 /* Resource closed */ 148 #define H_NOT_AVAILABLE 3 149 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 150 #define H_PARTIAL 5 151 #define H_IN_PROGRESS 14 /* Kind of like busy */ 152 #define H_PAGE_REGISTERED 15 153 #define H_PARTIAL_STORE 16 154 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 155 #define H_CONTINUE 18 /* Returned from H_Join on success */ 156 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 157 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 158 is a good time to retry */ 159 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 160 is a good time to retry */ 161 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 162 is a good time to retry */ 163 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 164 is a good time to retry */ 165 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 166 is a good time to retry */ 167 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 168 is a good time to retry */ 169 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 170 #define H_HARDWARE -1 /* Hardware error */ 171 #define H_FUNCTION -2 /* Function not supported */ 172 #define H_PRIVILEGE -3 /* Caller not privileged */ 173 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 174 #define H_BAD_MODE -5 /* Illegal msr value */ 175 #define H_PTEG_FULL -6 /* PTEG is full */ 176 #define H_NOT_FOUND -7 /* PTE was not found" */ 177 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 178 #define H_NO_MEM -9 179 #define H_AUTHORITY -10 180 #define H_PERMISSION -11 181 #define H_DROPPED -12 182 #define H_SOURCE_PARM -13 183 #define H_DEST_PARM -14 184 #define H_REMOTE_PARM -15 185 #define H_RESOURCE -16 186 #define H_ADAPTER_PARM -17 187 #define H_RH_PARM -18 188 #define H_RCQ_PARM -19 189 #define H_SCQ_PARM -20 190 #define H_EQ_PARM -21 191 #define H_RT_PARM -22 192 #define H_ST_PARM -23 193 #define H_SIGT_PARM -24 194 #define H_TOKEN_PARM -25 195 #define H_MLENGTH_PARM -27 196 #define H_MEM_PARM -28 197 #define H_MEM_ACCESS_PARM -29 198 #define H_ATTR_PARM -30 199 #define H_PORT_PARM -31 200 #define H_MCG_PARM -32 201 #define H_VL_PARM -33 202 #define H_TSIZE_PARM -34 203 #define H_TRACE_PARM -35 204 205 #define H_MASK_PARM -37 206 #define H_MCG_FULL -38 207 #define H_ALIAS_EXIST -39 208 #define H_P_COUNTER -40 209 #define H_TABLE_FULL -41 210 #define H_ALT_TABLE -42 211 #define H_MR_CONDITION -43 212 #define H_NOT_ENOUGH_RESOURCES -44 213 #define H_R_STATE -45 214 #define H_RESCINDEND -46 215 #define H_P2 -55 216 #define H_P3 -56 217 #define H_P4 -57 218 #define H_P5 -58 219 #define H_P6 -59 220 #define H_P7 -60 221 #define H_P8 -61 222 #define H_P9 -62 223 #define H_UNSUPPORTED_FLAG -256 224 #define H_MULTI_THREADS_ACTIVE -9005 225 226 227 /* Long Busy is a condition that can be returned by the firmware 228 * when a call cannot be completed now, but the identical call 229 * should be retried later. This prevents calls blocking in the 230 * firmware for long periods of time. Annoyingly the firmware can return 231 * a range of return codes, hinting at how long we should wait before 232 * retrying. If you don't care for the hint, the macro below is a good 233 * way to check for the long_busy return codes 234 */ 235 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 236 && (x <= H_LONG_BUSY_END_RANGE)) 237 238 /* Flags */ 239 #define H_LARGE_PAGE (1ULL<<(63-16)) 240 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 241 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 242 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 243 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 244 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 245 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 246 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 247 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 248 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 249 #define H_ANDCOND (1ULL<<(63-33)) 250 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 251 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 252 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 253 #define H_COPY_PAGE (1ULL<<(63-49)) 254 #define H_N (1ULL<<(63-61)) 255 #define H_PP1 (1ULL<<(63-62)) 256 #define H_PP2 (1ULL<<(63-63)) 257 258 /* Values for 2nd argument to H_SET_MODE */ 259 #define H_SET_MODE_RESOURCE_SET_CIABR 1 260 #define H_SET_MODE_RESOURCE_SET_DAWR 2 261 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 262 #define H_SET_MODE_RESOURCE_LE 4 263 264 /* Flags for H_SET_MODE_RESOURCE_LE */ 265 #define H_SET_MODE_ENDIAN_BIG 0 266 #define H_SET_MODE_ENDIAN_LITTLE 1 267 268 /* VASI States */ 269 #define H_VASI_INVALID 0 270 #define H_VASI_ENABLED 1 271 #define H_VASI_ABORTED 2 272 #define H_VASI_SUSPENDING 3 273 #define H_VASI_SUSPENDED 4 274 #define H_VASI_RESUMED 5 275 #define H_VASI_COMPLETED 6 276 277 /* DABRX flags */ 278 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 279 #define H_DABRX_KERNEL (1ULL<<(63-62)) 280 #define H_DABRX_USER (1ULL<<(63-63)) 281 282 /* Each control block has to be on a 4K boundary */ 283 #define H_CB_ALIGNMENT 4096 284 285 /* pSeries hypervisor opcodes */ 286 #define H_REMOVE 0x04 287 #define H_ENTER 0x08 288 #define H_READ 0x0c 289 #define H_CLEAR_MOD 0x10 290 #define H_CLEAR_REF 0x14 291 #define H_PROTECT 0x18 292 #define H_GET_TCE 0x1c 293 #define H_PUT_TCE 0x20 294 #define H_SET_SPRG0 0x24 295 #define H_SET_DABR 0x28 296 #define H_PAGE_INIT 0x2c 297 #define H_SET_ASR 0x30 298 #define H_ASR_ON 0x34 299 #define H_ASR_OFF 0x38 300 #define H_LOGICAL_CI_LOAD 0x3c 301 #define H_LOGICAL_CI_STORE 0x40 302 #define H_LOGICAL_CACHE_LOAD 0x44 303 #define H_LOGICAL_CACHE_STORE 0x48 304 #define H_LOGICAL_ICBI 0x4c 305 #define H_LOGICAL_DCBF 0x50 306 #define H_GET_TERM_CHAR 0x54 307 #define H_PUT_TERM_CHAR 0x58 308 #define H_REAL_TO_LOGICAL 0x5c 309 #define H_HYPERVISOR_DATA 0x60 310 #define H_EOI 0x64 311 #define H_CPPR 0x68 312 #define H_IPI 0x6c 313 #define H_IPOLL 0x70 314 #define H_XIRR 0x74 315 #define H_PERFMON 0x7c 316 #define H_MIGRATE_DMA 0x78 317 #define H_REGISTER_VPA 0xDC 318 #define H_CEDE 0xE0 319 #define H_CONFER 0xE4 320 #define H_PROD 0xE8 321 #define H_GET_PPP 0xEC 322 #define H_SET_PPP 0xF0 323 #define H_PURR 0xF4 324 #define H_PIC 0xF8 325 #define H_REG_CRQ 0xFC 326 #define H_FREE_CRQ 0x100 327 #define H_VIO_SIGNAL 0x104 328 #define H_SEND_CRQ 0x108 329 #define H_COPY_RDMA 0x110 330 #define H_REGISTER_LOGICAL_LAN 0x114 331 #define H_FREE_LOGICAL_LAN 0x118 332 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 333 #define H_SEND_LOGICAL_LAN 0x120 334 #define H_BULK_REMOVE 0x124 335 #define H_MULTICAST_CTRL 0x130 336 #define H_SET_XDABR 0x134 337 #define H_STUFF_TCE 0x138 338 #define H_PUT_TCE_INDIRECT 0x13C 339 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 340 #define H_VTERM_PARTNER_INFO 0x150 341 #define H_REGISTER_VTERM 0x154 342 #define H_FREE_VTERM 0x158 343 #define H_RESET_EVENTS 0x15C 344 #define H_ALLOC_RESOURCE 0x160 345 #define H_FREE_RESOURCE 0x164 346 #define H_MODIFY_QP 0x168 347 #define H_QUERY_QP 0x16C 348 #define H_REREGISTER_PMR 0x170 349 #define H_REGISTER_SMR 0x174 350 #define H_QUERY_MR 0x178 351 #define H_QUERY_MW 0x17C 352 #define H_QUERY_HCA 0x180 353 #define H_QUERY_PORT 0x184 354 #define H_MODIFY_PORT 0x188 355 #define H_DEFINE_AQP1 0x18C 356 #define H_GET_TRACE_BUFFER 0x190 357 #define H_DEFINE_AQP0 0x194 358 #define H_RESIZE_MR 0x198 359 #define H_ATTACH_MCQP 0x19C 360 #define H_DETACH_MCQP 0x1A0 361 #define H_CREATE_RPT 0x1A4 362 #define H_REMOVE_RPT 0x1A8 363 #define H_REGISTER_RPAGES 0x1AC 364 #define H_DISABLE_AND_GETC 0x1B0 365 #define H_ERROR_DATA 0x1B4 366 #define H_GET_HCA_INFO 0x1B8 367 #define H_GET_PERF_COUNT 0x1BC 368 #define H_MANAGE_TRACE 0x1C0 369 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 370 #define H_QUERY_INT_STATE 0x1E4 371 #define H_POLL_PENDING 0x1D8 372 #define H_ILLAN_ATTRIBUTES 0x244 373 #define H_MODIFY_HEA_QP 0x250 374 #define H_QUERY_HEA_QP 0x254 375 #define H_QUERY_HEA 0x258 376 #define H_QUERY_HEA_PORT 0x25C 377 #define H_MODIFY_HEA_PORT 0x260 378 #define H_REG_BCMC 0x264 379 #define H_DEREG_BCMC 0x268 380 #define H_REGISTER_HEA_RPAGES 0x26C 381 #define H_DISABLE_AND_GET_HEA 0x270 382 #define H_GET_HEA_INFO 0x274 383 #define H_ALLOC_HEA_RESOURCE 0x278 384 #define H_ADD_CONN 0x284 385 #define H_DEL_CONN 0x288 386 #define H_JOIN 0x298 387 #define H_VASI_STATE 0x2A4 388 #define H_ENABLE_CRQ 0x2B0 389 #define H_GET_EM_PARMS 0x2B8 390 #define H_SET_MPP 0x2D0 391 #define H_GET_MPP 0x2D4 392 #define H_XIRR_X 0x2FC 393 #define H_RANDOM 0x300 394 #define H_SET_MODE 0x31C 395 #define H_RESIZE_HPT_PREPARE 0x36C 396 #define H_RESIZE_HPT_COMMIT 0x370 397 #define H_CLEAN_SLB 0x374 398 #define H_INVALIDATE_PID 0x378 399 #define H_REGISTER_PROC_TBL 0x37C 400 #define H_SIGNAL_SYS_RESET 0x380 401 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET 402 403 /* The hcalls above are standardized in PAPR and implemented by pHyp 404 * as well. 405 * 406 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 407 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 408 * for "platform-specific" hcalls. 409 */ 410 #define KVMPPC_HCALL_BASE 0xf000 411 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 412 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 413 /* Client Architecture support */ 414 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 415 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 416 417 typedef struct sPAPRDeviceTreeUpdateHeader { 418 uint32_t version_id; 419 } sPAPRDeviceTreeUpdateHeader; 420 421 #define hcall_dprintf(fmt, ...) \ 422 do { \ 423 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 424 } while (0) 425 426 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 427 target_ulong opcode, 428 target_ulong *args); 429 430 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 431 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 432 target_ulong *args); 433 434 /* ibm,set-eeh-option */ 435 #define RTAS_EEH_DISABLE 0 436 #define RTAS_EEH_ENABLE 1 437 #define RTAS_EEH_THAW_IO 2 438 #define RTAS_EEH_THAW_DMA 3 439 440 /* ibm,get-config-addr-info2 */ 441 #define RTAS_GET_PE_ADDR 0 442 #define RTAS_GET_PE_MODE 1 443 #define RTAS_PE_MODE_NONE 0 444 #define RTAS_PE_MODE_NOT_SHARED 1 445 #define RTAS_PE_MODE_SHARED 2 446 447 /* ibm,read-slot-reset-state2 */ 448 #define RTAS_EEH_PE_STATE_NORMAL 0 449 #define RTAS_EEH_PE_STATE_RESET 1 450 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 451 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 452 #define RTAS_EEH_PE_STATE_UNAVAIL 5 453 #define RTAS_EEH_NOT_SUPPORT 0 454 #define RTAS_EEH_SUPPORT 1 455 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 456 #define RTAS_EEH_PE_RECOVER_INFO 0 457 458 /* ibm,set-slot-reset */ 459 #define RTAS_SLOT_RESET_DEACTIVATE 0 460 #define RTAS_SLOT_RESET_HOT 1 461 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 462 463 /* ibm,slot-error-detail */ 464 #define RTAS_SLOT_TEMP_ERR_LOG 1 465 #define RTAS_SLOT_PERM_ERR_LOG 2 466 467 /* RTAS return codes */ 468 #define RTAS_OUT_SUCCESS 0 469 #define RTAS_OUT_NO_ERRORS_FOUND 1 470 #define RTAS_OUT_HW_ERROR -1 471 #define RTAS_OUT_BUSY -2 472 #define RTAS_OUT_PARAM_ERROR -3 473 #define RTAS_OUT_NOT_SUPPORTED -3 474 #define RTAS_OUT_NO_SUCH_INDICATOR -3 475 #define RTAS_OUT_NOT_AUTHORIZED -9002 476 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 477 478 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 479 #define RTAS_DDW_PGSIZE_4K 0x01 480 #define RTAS_DDW_PGSIZE_64K 0x02 481 #define RTAS_DDW_PGSIZE_16M 0x04 482 #define RTAS_DDW_PGSIZE_32M 0x08 483 #define RTAS_DDW_PGSIZE_64M 0x10 484 #define RTAS_DDW_PGSIZE_128M 0x20 485 #define RTAS_DDW_PGSIZE_256M 0x40 486 #define RTAS_DDW_PGSIZE_16G 0x80 487 488 /* RTAS tokens */ 489 #define RTAS_TOKEN_BASE 0x2000 490 491 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 492 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 493 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 494 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 495 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 496 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 497 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 498 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 499 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 500 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 501 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 502 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 503 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 504 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 505 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 506 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 507 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 508 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 509 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 510 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 511 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 512 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 513 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 514 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 515 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 516 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 517 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 518 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 519 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 520 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 521 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 522 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 523 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 524 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 525 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 526 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 527 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 528 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 529 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 530 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 531 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 532 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 533 534 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 535 536 /* RTAS ibm,get-system-parameter token values */ 537 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 538 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 539 #define RTAS_SYSPARM_UUID 48 540 541 /* RTAS indicator/sensor types 542 * 543 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 544 * 545 * NOTE: currently only DR-related sensors are implemented here 546 */ 547 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 548 #define RTAS_SENSOR_TYPE_DR 9002 549 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 550 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 551 552 /* Possible values for the platform-processor-diagnostics-run-mode parameter 553 * of the RTAS ibm,get-system-parameter call. 554 */ 555 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 556 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 557 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 558 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 559 560 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 561 { 562 return addr & ~0xF000000000000000ULL; 563 } 564 565 static inline uint32_t rtas_ld(target_ulong phys, int n) 566 { 567 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 568 } 569 570 static inline uint64_t rtas_ldq(target_ulong phys, int n) 571 { 572 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 573 } 574 575 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 576 { 577 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 578 } 579 580 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 581 uint32_t token, 582 uint32_t nargs, target_ulong args, 583 uint32_t nret, target_ulong rets); 584 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 585 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 586 uint32_t token, uint32_t nargs, target_ulong args, 587 uint32_t nret, target_ulong rets); 588 void spapr_dt_rtas_tokens(void *fdt, int rtas); 589 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 590 591 #define SPAPR_TCE_PAGE_SHIFT 12 592 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 593 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 594 595 #define SPAPR_VIO_BASE_LIOBN 0x00000000 596 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 597 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 598 (0x80000000 | ((phb_index) << 8) | (window_num)) 599 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 600 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 601 602 #define RTAS_ERROR_LOG_MAX 2048 603 604 #define RTAS_EVENT_SCAN_RATE 1 605 606 /* This helper should be used to encode interrupt specifiers when the related 607 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 608 * VIO devices, RTAS event sources and PHBs). 609 */ 610 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi) 611 { 612 intspec[0] = cpu_to_be32(irq); 613 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 614 } 615 616 typedef struct sPAPRTCETable sPAPRTCETable; 617 618 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 619 #define SPAPR_TCE_TABLE(obj) \ 620 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 621 622 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 623 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 624 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 625 626 struct sPAPRTCETable { 627 DeviceState parent; 628 uint32_t liobn; 629 uint32_t nb_table; 630 uint64_t bus_offset; 631 uint32_t page_shift; 632 uint64_t *table; 633 uint32_t mig_nb_table; 634 uint64_t *mig_table; 635 bool bypass; 636 bool need_vfio; 637 int fd; 638 MemoryRegion root; 639 IOMMUMemoryRegion iommu; 640 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 641 QLIST_ENTRY(sPAPRTCETable) list; 642 }; 643 644 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 645 646 struct sPAPREventLogEntry { 647 uint32_t summary; 648 uint32_t extended_length; 649 void *extended_log; 650 QTAILQ_ENTRY(sPAPREventLogEntry) next; 651 }; 652 653 void spapr_events_init(sPAPRMachineState *sm); 654 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 655 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 656 target_ulong addr, target_ulong size, 657 sPAPROptionVector *ov5_updates); 658 void close_htab_fd(sPAPRMachineState *spapr); 659 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 660 void spapr_free_hpt(sPAPRMachineState *spapr); 661 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 662 void spapr_tce_table_enable(sPAPRTCETable *tcet, 663 uint32_t page_shift, uint64_t bus_offset, 664 uint32_t nb_table); 665 void spapr_tce_table_disable(sPAPRTCETable *tcet); 666 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 667 668 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 669 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 670 uint32_t liobn, uint64_t window, uint32_t size); 671 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 672 sPAPRTCETable *tcet); 673 void spapr_pci_switch_vga(bool big_endian); 674 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 675 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 676 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 677 uint32_t count); 678 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 679 uint32_t count); 680 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 681 uint32_t count, uint32_t index); 682 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 683 uint32_t count, uint32_t index); 684 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 685 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 686 Error **errp); 687 void spapr_clear_pending_events(sPAPRMachineState *spapr); 688 689 /* CPU and LMB DRC release callbacks. */ 690 void spapr_core_release(DeviceState *dev); 691 void spapr_lmb_release(DeviceState *dev); 692 693 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 694 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 695 696 #define TYPE_SPAPR_RNG "spapr-rng" 697 698 int spapr_rng_populate_dt(void *fdt); 699 700 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 701 702 /* 703 * This defines the maximum number of DIMM slots we can have for sPAPR 704 * guest. This is not defined by sPAPR but we are defining it to 32 slots 705 * based on default number of slots provided by PowerPC kernel. 706 */ 707 #define SPAPR_MAX_RAM_SLOTS 32 708 709 /* 1GB alignment for hotplug memory region */ 710 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 711 712 /* 713 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 714 * property under ibm,dynamic-reconfiguration-memory node. 715 */ 716 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 717 718 /* 719 * Defines for flag value in ibm,dynamic-memory property under 720 * ibm,dynamic-reconfiguration-memory node. 721 */ 722 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 723 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 724 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 725 726 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 727 728 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 729 730 int spapr_vcpu_id(PowerPCCPU *cpu); 731 PowerPCCPU *spapr_find_cpu(int vcpu_id); 732 733 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 734 Error **errp); 735 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 736 bool align, Error **errp); 737 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); 738 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); 739 740 /* 741 * Handling of optional capabilities 742 */ 743 static inline sPAPRCapabilities spapr_caps(uint64_t mask) 744 { 745 sPAPRCapabilities caps = { mask }; 746 return caps; 747 } 748 749 static inline bool spapr_has_cap(sPAPRMachineState *spapr, uint64_t cap) 750 { 751 return !!(spapr->effective_caps.mask & cap); 752 } 753 754 void spapr_caps_reset(sPAPRMachineState *spapr); 755 void spapr_caps_validate(sPAPRMachineState *spapr, Error **errp); 756 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); 757 758 #endif /* HW_SPAPR_H */ 759