1 /* 2 * QEMU PowerPC 4xx emulation shared definitions 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC4XX_H 26 #define PPC4XX_H 27 28 #include "hw/ppc/ppc.h" 29 #include "exec/memory.h" 30 #include "hw/sysbus.h" 31 32 #define TYPE_PPC4xx_PCI_HOST "ppc4xx-pci-host" 33 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" 34 35 /* 36 * Generic DCR device 37 */ 38 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device" 39 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE); 40 struct Ppc4xxDcrDeviceState { 41 SysBusDevice parent_obj; 42 43 PowerPCCPU *cpu; 44 }; 45 46 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 47 dcr_read_cb dcr_read, dcr_write_cb dcr_write); 48 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 49 Error **errp); 50 51 /* Memory Access Layer (MAL) */ 52 #define TYPE_PPC4xx_MAL "ppc4xx-mal" 53 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL); 54 struct Ppc4xxMalState { 55 Ppc4xxDcrDeviceState parent_obj; 56 57 qemu_irq irqs[4]; 58 uint32_t cfg; 59 uint32_t esr; 60 uint32_t ier; 61 uint32_t txcasr; 62 uint32_t txcarr; 63 uint32_t txeobisr; 64 uint32_t txdeir; 65 uint32_t rxcasr; 66 uint32_t rxcarr; 67 uint32_t rxeobisr; 68 uint32_t rxdeir; 69 uint32_t *txctpr; 70 uint32_t *rxctpr; 71 uint32_t *rcbs; 72 uint8_t txcnum; 73 uint8_t rxcnum; 74 }; 75 76 /* Peripheral local bus arbitrer */ 77 #define TYPE_PPC4xx_PLB "ppc4xx-plb" 78 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB); 79 struct Ppc4xxPlbState { 80 Ppc4xxDcrDeviceState parent_obj; 81 82 uint32_t acr; 83 uint32_t bear; 84 uint32_t besr; 85 }; 86 87 /* Peripheral controller */ 88 #define TYPE_PPC4xx_EBC "ppc4xx-ebc" 89 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC); 90 struct Ppc4xxEbcState { 91 Ppc4xxDcrDeviceState parent_obj; 92 93 uint32_t addr; 94 uint32_t bcr[8]; 95 uint32_t bap[8]; 96 uint32_t bear; 97 uint32_t besr0; 98 uint32_t besr1; 99 uint32_t cfg; 100 }; 101 102 /* SDRAM DDR controller */ 103 typedef struct { 104 MemoryRegion ram; 105 MemoryRegion container; /* used for clipping */ 106 hwaddr base; 107 hwaddr size; 108 uint32_t bcr; 109 } Ppc4xxSdramBank; 110 111 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) 112 #define SDR0_DDR0_DDRM_DDR1 0x20000000 113 #define SDR0_DDR0_DDRM_DDR2 0x40000000 114 115 #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr" 116 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR); 117 struct Ppc4xxSdramDdrState { 118 Ppc4xxDcrDeviceState parent_obj; 119 120 MemoryRegion *dram_mr; 121 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 122 Ppc4xxSdramBank bank[4]; 123 qemu_irq irq; 124 125 uint32_t addr; 126 uint32_t besr0; 127 uint32_t besr1; 128 uint32_t bear; 129 uint32_t cfg; 130 uint32_t status; 131 uint32_t rtr; 132 uint32_t pmit; 133 uint32_t tr; 134 uint32_t ecccfg; 135 uint32_t eccesr; 136 }; 137 138 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s); 139 140 /* SDRAM DDR2 controller */ 141 #define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2" 142 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2); 143 struct Ppc4xxSdramDdr2State { 144 Ppc4xxDcrDeviceState parent_obj; 145 146 MemoryRegion *dram_mr; 147 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ 148 Ppc4xxSdramBank bank[4]; 149 150 uint32_t addr; 151 uint32_t mcopt2; 152 }; 153 154 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s); 155 156 #endif /* PPC4XX_H */ 157