1 /* 2 * QEMU PowerPC 4xx emulation shared definitions 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC4XX_H 26 #define PPC4XX_H 27 28 #include "hw/ppc/ppc.h" 29 #include "exec/memory.h" 30 #include "hw/sysbus.h" 31 32 typedef struct { 33 MemoryRegion ram; 34 MemoryRegion container; /* used for clipping */ 35 hwaddr base; 36 hwaddr size; 37 uint32_t bcr; 38 } Ppc4xxSdramBank; 39 40 void ppc4xx_sdram_enable(CPUPPCState *env); 41 42 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 43 Ppc4xxSdramBank ram_banks[], 44 const ram_addr_t sdram_bank_sizes[]); 45 46 void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, 47 MemoryRegion *ram); 48 49 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" 50 51 /* 52 * Generic DCR device 53 */ 54 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device" 55 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE); 56 struct Ppc4xxDcrDeviceState { 57 SysBusDevice parent_obj; 58 59 PowerPCCPU *cpu; 60 }; 61 62 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 63 dcr_read_cb dcr_read, dcr_write_cb dcr_write); 64 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 65 Error **errp); 66 67 /* Memory Access Layer (MAL) */ 68 #define TYPE_PPC4xx_MAL "ppc4xx-mal" 69 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL); 70 struct Ppc4xxMalState { 71 Ppc4xxDcrDeviceState parent_obj; 72 73 qemu_irq irqs[4]; 74 uint32_t cfg; 75 uint32_t esr; 76 uint32_t ier; 77 uint32_t txcasr; 78 uint32_t txcarr; 79 uint32_t txeobisr; 80 uint32_t txdeir; 81 uint32_t rxcasr; 82 uint32_t rxcarr; 83 uint32_t rxeobisr; 84 uint32_t rxdeir; 85 uint32_t *txctpr; 86 uint32_t *rxctpr; 87 uint32_t *rcbs; 88 uint8_t txcnum; 89 uint8_t rxcnum; 90 }; 91 92 /* Peripheral local bus arbitrer */ 93 #define TYPE_PPC4xx_PLB "ppc4xx-plb" 94 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB); 95 struct Ppc4xxPlbState { 96 Ppc4xxDcrDeviceState parent_obj; 97 98 uint32_t acr; 99 uint32_t bear; 100 uint32_t besr; 101 }; 102 103 /* Peripheral controller */ 104 #define TYPE_PPC4xx_EBC "ppc4xx-ebc" 105 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC); 106 struct Ppc4xxEbcState { 107 Ppc4xxDcrDeviceState parent_obj; 108 109 uint32_t addr; 110 uint32_t bcr[8]; 111 uint32_t bap[8]; 112 uint32_t bear; 113 uint32_t besr0; 114 uint32_t besr1; 115 uint32_t cfg; 116 }; 117 118 #endif /* PPC4XX_H */ 119