1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2.1 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_CORE_H 21 #define PPC_PNV_CORE_H 22 23 #include "hw/cpu/core.h" 24 #include "target/ppc/cpu.h" 25 #include "hw/ppc/pnv.h" 26 #include "qom/object.h" 27 28 /* Per-core ChipTOD / TimeBase state */ 29 typedef struct PnvCoreTODState { 30 int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ 31 int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ 32 33 /* 34 * "Timers" for async TBST events are simulated by mfTFAC because TFAC 35 * is polled for such events. These are just used to ensure firmware 36 * performs the polling at least a few times. 37 */ 38 int tb_state_timer; 39 int tb_sync_pulse_timer; 40 } PnvCoreTODState; 41 42 #define TYPE_PNV_CORE "powernv-cpu-core" 43 OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass, 44 PNV_CORE) 45 46 struct PnvCore { 47 /*< private >*/ 48 CPUCore parent_obj; 49 50 /*< public >*/ 51 PowerPCCPU **threads; 52 uint32_t pir; 53 uint32_t hwid; 54 uint64_t hrmor; 55 56 PnvCoreTODState tod_state; 57 58 PnvChip *chip; 59 60 MemoryRegion xscom_regs; 61 }; 62 63 struct PnvCoreClass { 64 DeviceClass parent_class; 65 66 const MemoryRegionOps *xscom_ops; 67 uint64_t xscom_size; 68 }; 69 70 #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE 71 #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX 72 73 typedef struct PnvCPUState { 74 PnvCore *pnv_core; 75 Object *intc; 76 } PnvCPUState; 77 78 static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu) 79 { 80 return (PnvCPUState *)cpu->machine_data; 81 } 82 83 struct PnvQuadClass { 84 DeviceClass parent_class; 85 86 const MemoryRegionOps *xscom_ops; 87 uint64_t xscom_size; 88 89 const MemoryRegionOps *xscom_qme_ops; 90 uint64_t xscom_qme_size; 91 }; 92 93 #define TYPE_PNV_QUAD "powernv-cpu-quad" 94 95 #define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD 96 #define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX 97 98 OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD) 99 100 struct PnvQuad { 101 DeviceState parent_obj; 102 103 uint32_t quad_id; 104 MemoryRegion xscom_regs; 105 MemoryRegion xscom_qme_regs; 106 }; 107 #endif /* PPC_PNV_CORE_H */ 108