1 #ifndef PPC_PNV_CHIP_H 2 #define PPC_PNV_CHIP_H 3 4 #include "hw/pci-host/pnv_phb4.h" 5 #include "hw/ppc/pnv_core.h" 6 #include "hw/ppc/pnv_homer.h" 7 #include "hw/ppc/pnv_n1_chiplet.h" 8 #include "hw/ppc/pnv_lpc.h" 9 #include "hw/ppc/pnv_occ.h" 10 #include "hw/ppc/pnv_psi.h" 11 #include "hw/ppc/pnv_sbe.h" 12 #include "hw/ppc/pnv_xive.h" 13 #include "hw/ppc/pnv_i2c.h" 14 #include "hw/sysbus.h" 15 16 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 17 PNV_CHIP) 18 19 struct PnvChip { 20 /*< private >*/ 21 SysBusDevice parent_obj; 22 23 /*< public >*/ 24 uint32_t chip_id; 25 uint64_t ram_start; 26 uint64_t ram_size; 27 28 uint32_t nr_cores; 29 uint32_t nr_threads; 30 uint64_t cores_mask; 31 PnvCore **cores; 32 33 uint32_t num_pecs; 34 35 MemoryRegion xscom_mmio; 36 MemoryRegion xscom; 37 AddressSpace xscom_as; 38 39 MemoryRegion *fw_mr; 40 gchar *dt_isa_nodename; 41 }; 42 43 #define TYPE_PNV8_CHIP "pnv8-chip" 44 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 45 TYPE_PNV8_CHIP) 46 47 struct Pnv8Chip { 48 /*< private >*/ 49 PnvChip parent_obj; 50 51 /*< public >*/ 52 MemoryRegion icp_mmio; 53 54 PnvLpcController lpc; 55 Pnv8Psi psi; 56 PnvOCC occ; 57 PnvHomer homer; 58 59 #define PNV8_CHIP_PHB3_MAX 4 60 /* 61 * The array is used to allow quick access to the phbs by 62 * pnv_ics_get_child() and pnv_ics_resend_child(). 63 */ 64 PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; 65 uint32_t num_phbs; 66 67 XICSFabric *xics; 68 }; 69 70 #define TYPE_PNV9_CHIP "pnv9-chip" 71 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 72 TYPE_PNV9_CHIP) 73 74 struct Pnv9Chip { 75 /*< private >*/ 76 PnvChip parent_obj; 77 78 /*< public >*/ 79 PnvXive xive; 80 Pnv9Psi psi; 81 PnvLpcController lpc; 82 PnvOCC occ; 83 PnvSBE sbe; 84 PnvHomer homer; 85 86 uint32_t nr_quads; 87 PnvQuad *quads; 88 89 #define PNV9_CHIP_MAX_PEC 3 90 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 91 92 #define PNV9_CHIP_MAX_I2C 4 93 PnvI2C i2c[PNV9_CHIP_MAX_I2C]; 94 }; 95 96 /* 97 * A SMT8 fused core is a pair of SMT4 cores. 98 */ 99 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 100 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 101 102 #define TYPE_PNV10_CHIP "pnv10-chip" 103 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 104 TYPE_PNV10_CHIP) 105 106 struct Pnv10Chip { 107 /*< private >*/ 108 PnvChip parent_obj; 109 110 /*< public >*/ 111 PnvXive2 xive; 112 Pnv9Psi psi; 113 PnvLpcController lpc; 114 PnvOCC occ; 115 PnvSBE sbe; 116 PnvHomer homer; 117 PnvN1Chiplet n1_chiplet; 118 119 uint32_t nr_quads; 120 PnvQuad *quads; 121 122 #define PNV10_CHIP_MAX_PEC 2 123 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; 124 125 #define PNV10_CHIP_MAX_I2C 4 126 PnvI2C i2c[PNV10_CHIP_MAX_I2C]; 127 }; 128 129 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 130 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 131 132 struct PnvChipClass { 133 /*< private >*/ 134 SysBusDeviceClass parent_class; 135 136 /*< public >*/ 137 uint64_t chip_cfam_id; 138 uint64_t cores_mask; 139 uint32_t num_pecs; 140 uint32_t num_phbs; 141 142 uint32_t i2c_num_engines; 143 const int *i2c_ports_per_engine; 144 145 DeviceRealize parent_realize; 146 147 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 148 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 149 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 150 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 151 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 152 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 153 void (*dt_populate)(PnvChip *chip, void *fdt); 154 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 155 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 156 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 157 }; 158 159 #endif 160