1 #ifndef PPC_PNV_CHIP_H 2 #define PPC_PNV_CHIP_H 3 4 #include "hw/pci-host/pnv_phb4.h" 5 #include "hw/ppc/pnv_adu.h" 6 #include "hw/ppc/pnv_chiptod.h" 7 #include "hw/ppc/pnv_core.h" 8 #include "hw/ppc/pnv_homer.h" 9 #include "hw/ppc/pnv_n1_chiplet.h" 10 #include "hw/ppc/pnv_lpc.h" 11 #include "hw/ppc/pnv_occ.h" 12 #include "hw/ppc/pnv_psi.h" 13 #include "hw/ppc/pnv_sbe.h" 14 #include "hw/ppc/pnv_xive.h" 15 #include "hw/ppc/pnv_i2c.h" 16 #include "hw/sysbus.h" 17 18 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 19 PNV_CHIP) 20 21 struct PnvChip { 22 /*< private >*/ 23 SysBusDevice parent_obj; 24 25 /*< public >*/ 26 uint32_t chip_id; 27 uint64_t ram_start; 28 uint64_t ram_size; 29 30 uint32_t nr_cores; 31 uint32_t nr_threads; 32 uint64_t cores_mask; 33 PnvCore **cores; 34 35 uint32_t num_pecs; 36 37 MemoryRegion xscom_mmio; 38 MemoryRegion xscom; 39 AddressSpace xscom_as; 40 41 MemoryRegion *fw_mr; 42 gchar *dt_isa_nodename; 43 }; 44 45 #define TYPE_PNV8_CHIP "pnv8-chip" 46 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 47 TYPE_PNV8_CHIP) 48 49 struct Pnv8Chip { 50 /*< private >*/ 51 PnvChip parent_obj; 52 53 /*< public >*/ 54 MemoryRegion icp_mmio; 55 56 PnvLpcController lpc; 57 Pnv8Psi psi; 58 PnvOCC occ; 59 PnvHomer homer; 60 61 #define PNV8_CHIP_PHB3_MAX 4 62 /* 63 * The array is used to allow quick access to the phbs by 64 * pnv_ics_get_child() and pnv_ics_resend_child(). 65 */ 66 PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; 67 uint32_t num_phbs; 68 69 XICSFabric *xics; 70 }; 71 72 #define TYPE_PNV9_CHIP "pnv9-chip" 73 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 74 TYPE_PNV9_CHIP) 75 76 struct Pnv9Chip { 77 /*< private >*/ 78 PnvChip parent_obj; 79 80 /*< public >*/ 81 PnvADU adu; 82 PnvXive xive; 83 Pnv9Psi psi; 84 PnvLpcController lpc; 85 PnvChipTOD chiptod; 86 PnvOCC occ; 87 PnvSBE sbe; 88 PnvHomer homer; 89 90 uint32_t nr_quads; 91 PnvQuad *quads; 92 93 #define PNV9_CHIP_MAX_PEC 3 94 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 95 96 #define PNV9_CHIP_MAX_I2C 4 97 PnvI2C i2c[PNV9_CHIP_MAX_I2C]; 98 }; 99 100 /* 101 * A SMT8 fused core is a pair of SMT4 cores. 102 */ 103 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 104 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 105 106 #define TYPE_PNV10_CHIP "pnv10-chip" 107 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 108 TYPE_PNV10_CHIP) 109 110 struct Pnv10Chip { 111 /*< private >*/ 112 PnvChip parent_obj; 113 114 /*< public >*/ 115 PnvADU adu; 116 PnvXive2 xive; 117 Pnv9Psi psi; 118 PnvLpcController lpc; 119 PnvChipTOD chiptod; 120 PnvOCC occ; 121 PnvSBE sbe; 122 PnvHomer homer; 123 PnvN1Chiplet n1_chiplet; 124 125 uint32_t nr_quads; 126 PnvQuad *quads; 127 128 #define PNV10_CHIP_MAX_PEC 2 129 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; 130 131 #define PNV10_CHIP_MAX_I2C 4 132 PnvI2C i2c[PNV10_CHIP_MAX_I2C]; 133 }; 134 135 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 136 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 137 138 struct PnvChipClass { 139 /*< private >*/ 140 SysBusDeviceClass parent_class; 141 142 /*< public >*/ 143 uint64_t chip_cfam_id; 144 uint64_t cores_mask; 145 uint32_t num_pecs; 146 uint32_t num_phbs; 147 148 uint32_t i2c_num_engines; 149 const int *i2c_ports_per_engine; 150 151 DeviceRealize parent_realize; 152 153 /* Get PIR and TIR values for a CPU thread identified by core/thread id */ 154 void (*get_pir_tir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id, 155 uint32_t *pir, uint32_t *tir); 156 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 157 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 158 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 159 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf); 160 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 161 void (*dt_populate)(PnvChip *chip, void *fdt); 162 void (*pic_print_info)(PnvChip *chip, GString *buf); 163 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 164 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 165 }; 166 167 #endif 168