1 #ifndef PPC_PNV_CHIP_H 2 #define PPC_PNV_CHIP_H 3 4 #include "hw/pci-host/pnv_phb4.h" 5 #include "hw/ppc/pnv_core.h" 6 #include "hw/ppc/pnv_homer.h" 7 #include "hw/ppc/pnv_lpc.h" 8 #include "hw/ppc/pnv_occ.h" 9 #include "hw/ppc/pnv_psi.h" 10 #include "hw/ppc/pnv_sbe.h" 11 #include "hw/ppc/pnv_xive.h" 12 #include "hw/ppc/pnv_i2c.h" 13 #include "hw/sysbus.h" 14 15 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 16 PNV_CHIP) 17 18 struct PnvChip { 19 /*< private >*/ 20 SysBusDevice parent_obj; 21 22 /*< public >*/ 23 uint32_t chip_id; 24 uint64_t ram_start; 25 uint64_t ram_size; 26 27 uint32_t nr_cores; 28 uint32_t nr_threads; 29 uint64_t cores_mask; 30 PnvCore **cores; 31 32 uint32_t num_pecs; 33 34 MemoryRegion xscom_mmio; 35 MemoryRegion xscom; 36 AddressSpace xscom_as; 37 38 MemoryRegion *fw_mr; 39 gchar *dt_isa_nodename; 40 }; 41 42 #define TYPE_PNV8_CHIP "pnv8-chip" 43 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 44 TYPE_PNV8_CHIP) 45 46 struct Pnv8Chip { 47 /*< private >*/ 48 PnvChip parent_obj; 49 50 /*< public >*/ 51 MemoryRegion icp_mmio; 52 53 PnvLpcController lpc; 54 Pnv8Psi psi; 55 PnvOCC occ; 56 PnvHomer homer; 57 58 #define PNV8_CHIP_PHB3_MAX 4 59 /* 60 * The array is used to allow quick access to the phbs by 61 * pnv_ics_get_child() and pnv_ics_resend_child(). 62 */ 63 PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; 64 uint32_t num_phbs; 65 66 XICSFabric *xics; 67 }; 68 69 #define TYPE_PNV9_CHIP "pnv9-chip" 70 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 71 TYPE_PNV9_CHIP) 72 73 struct Pnv9Chip { 74 /*< private >*/ 75 PnvChip parent_obj; 76 77 /*< public >*/ 78 PnvXive xive; 79 Pnv9Psi psi; 80 PnvLpcController lpc; 81 PnvOCC occ; 82 PnvSBE sbe; 83 PnvHomer homer; 84 85 uint32_t nr_quads; 86 PnvQuad *quads; 87 88 #define PNV9_CHIP_MAX_PEC 3 89 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 90 91 #define PNV9_CHIP_MAX_I2C 3 92 #define PNV9_CHIP_MAX_I2C_PORTS 1 93 PnvI2C i2c[PNV9_CHIP_MAX_I2C]; 94 }; 95 96 /* 97 * A SMT8 fused core is a pair of SMT4 cores. 98 */ 99 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 100 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 101 102 #define TYPE_PNV10_CHIP "pnv10-chip" 103 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 104 TYPE_PNV10_CHIP) 105 106 struct Pnv10Chip { 107 /*< private >*/ 108 PnvChip parent_obj; 109 110 /*< public >*/ 111 PnvXive2 xive; 112 Pnv9Psi psi; 113 PnvLpcController lpc; 114 PnvOCC occ; 115 PnvSBE sbe; 116 PnvHomer homer; 117 118 uint32_t nr_quads; 119 PnvQuad *quads; 120 121 #define PNV10_CHIP_MAX_PEC 2 122 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; 123 124 #define PNV10_CHIP_MAX_I2C 4 125 #define PNV10_CHIP_MAX_I2C_PORTS 2 126 PnvI2C i2c[PNV10_CHIP_MAX_I2C]; 127 }; 128 129 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 130 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 131 132 struct PnvChipClass { 133 /*< private >*/ 134 SysBusDeviceClass parent_class; 135 136 /*< public >*/ 137 uint64_t chip_cfam_id; 138 uint64_t cores_mask; 139 uint32_t num_pecs; 140 uint32_t num_phbs; 141 142 uint32_t i2c_num_engines; 143 uint32_t i2c_num_ports; 144 145 DeviceRealize parent_realize; 146 147 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 148 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 149 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 150 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 151 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 152 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 153 void (*dt_populate)(PnvChip *chip, void *fdt); 154 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 155 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 156 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 157 }; 158 159 #endif 160