1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "cpu.h" 24 #include "hw/boards.h" 25 #include "hw/sysbus.h" 26 #include "hw/ipmi/ipmi.h" 27 #include "hw/ppc/pnv_pnor.h" 28 29 #define TYPE_PNV_CHIP "pnv-chip" 30 31 typedef struct PnvCore PnvCore; 32 typedef struct PnvChip PnvChip; 33 typedef struct Pnv8Chip Pnv8Chip; 34 typedef struct Pnv9Chip Pnv9Chip; 35 typedef struct Pnv10Chip Pnv10Chip; 36 37 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 38 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 39 40 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 41 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E, 42 TYPE_PNV_CHIP_POWER8E) 43 44 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 45 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, 46 TYPE_PNV_CHIP_POWER8) 47 48 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 49 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, 50 TYPE_PNV_CHIP_POWER8NVL) 51 52 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") 53 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, 54 TYPE_PNV_CHIP_POWER9) 55 56 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0") 57 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, 58 TYPE_PNV_CHIP_POWER10) 59 60 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id); 61 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 62 63 typedef struct PnvPHB PnvPHB; 64 65 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 66 typedef struct PnvMachineClass PnvMachineClass; 67 typedef struct PnvMachineState PnvMachineState; 68 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass, 69 PNV_MACHINE, TYPE_PNV_MACHINE) 70 71 72 struct PnvMachineClass { 73 /*< private >*/ 74 MachineClass parent_class; 75 76 /*< public >*/ 77 const char *compat; 78 int compat_size; 79 int max_smt_threads; 80 81 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 82 void (*i2c_init)(PnvMachineState *pnv); 83 }; 84 85 struct PnvMachineState { 86 /*< private >*/ 87 MachineState parent_obj; 88 89 uint32_t initrd_base; 90 long initrd_size; 91 92 uint32_t num_chips; 93 PnvChip **chips; 94 95 ISABus *isa_bus; 96 uint32_t cpld_irqstate; 97 98 IPMIBmc *bmc; 99 Notifier powerdown_notifier; 100 101 PnvPnor *pnor; 102 103 hwaddr fw_load_addr; 104 105 bool big_core; 106 }; 107 108 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id); 109 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb); 110 111 #define PNV_FDT_ADDR 0x01000000 112 #define PNV_TIMEBASE_FREQ 512000000ULL 113 114 /* 115 * BMC helpers 116 */ 117 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 118 void pnv_bmc_powerdown(IPMIBmc *bmc); 119 IPMIBmc *pnv_bmc_create(PnvPnor *pnor); 120 IPMIBmc *pnv_bmc_find(Error **errp); 121 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); 122 123 /* 124 * POWER8 MMIO base addresses 125 */ 126 #define PNV_XSCOM_SIZE 0x800000000ull 127 #define PNV_XSCOM_BASE(chip) \ 128 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 129 130 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 131 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 132 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 133 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 134 135 #define PNV_HOMER_SIZE 0x0000000000400000ull 136 #define PNV_HOMER_BASE(chip) \ 137 (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) 138 139 140 /* 141 * XSCOM 0x20109CA defines the ICP BAR: 142 * 143 * 0:29 : bits 14 to 43 of address to define 1 MB region. 144 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 145 * 31:63 : Constant 0 146 * 147 * Usually defined as : 148 * 149 * 0xffffe00200000000 -> 0x0003ffff80000000 150 * 0xffffe00600000000 -> 0x0003ffff80100000 151 * 0xffffe02200000000 -> 0x0003ffff80800000 152 * 0xffffe02600000000 -> 0x0003ffff80900000 153 */ 154 #define PNV_ICP_SIZE 0x0000000000100000ull 155 #define PNV_ICP_BASE(chip) \ 156 (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE) 157 158 159 #define PNV_PSIHB_SIZE 0x0000000000100000ull 160 #define PNV_PSIHB_BASE(chip) \ 161 (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE) 162 163 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 164 #define PNV_PSIHB_FSP_BASE(chip) \ 165 (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \ 166 PNV_PSIHB_FSP_SIZE) 167 168 /* 169 * POWER9 MMIO base addresses 170 */ 171 #define PNV9_CHIP_BASE(chip, base) \ 172 ((base) + ((uint64_t) (chip)->chip_id << 42)) 173 174 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 175 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 176 177 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 178 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 179 180 #define PNV9_LPCM_SIZE 0x0000000100000000ull 181 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 182 183 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 184 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 185 186 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 187 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 188 189 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 190 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 191 192 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 193 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 194 195 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 196 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 197 198 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 199 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 200 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 201 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 202 203 #define PNV9_HOMER_SIZE 0x0000000000400000ull 204 #define PNV9_HOMER_BASE(chip) \ 205 (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE) 206 207 /* 208 * POWER10 MMIO base addresses - 16TB stride per chip 209 */ 210 #define PNV10_CHIP_BASE(chip, base) \ 211 ((base) + ((uint64_t) (chip)->chip_id << 44)) 212 213 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 214 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 215 216 #define PNV10_LPCM_SIZE 0x0000000100000000ull 217 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 218 219 #define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull 220 #define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull) 221 222 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 223 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 224 225 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 226 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 227 228 #define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull 229 #define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull) 230 231 #define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull 232 #define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull) 233 234 #define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull 235 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull) 236 237 #define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull 238 #define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull) 239 240 #define PNV10_XIVE2_END_SIZE 0x0000020000000000ull 241 #define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull) 242 243 #define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 244 #define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull 245 #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \ 246 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 247 248 #define PNV10_HOMER_SIZE 0x0000000000400000ull 249 #define PNV10_HOMER_BASE(chip) \ 250 (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE) 251 252 #endif /* PPC_PNV_H */ 253