1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef _PPC_PNV_H 20 #define _PPC_PNV_H 21 22 #include "hw/boards.h" 23 #include "hw/sysbus.h" 24 25 #define TYPE_PNV_CHIP "powernv-chip" 26 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 27 #define PNV_CHIP_CLASS(klass) \ 28 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 29 #define PNV_CHIP_GET_CLASS(obj) \ 30 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 31 32 typedef enum PnvChipType { 33 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 34 PNV_CHIP_POWER8, /* AKA Venice */ 35 PNV_CHIP_POWER8NVL, /* AKA Naples */ 36 PNV_CHIP_POWER9, /* AKA Nimbus */ 37 } PnvChipType; 38 39 typedef struct PnvChip { 40 /*< private >*/ 41 SysBusDevice parent_obj; 42 43 /*< public >*/ 44 uint32_t chip_id; 45 uint64_t ram_start; 46 uint64_t ram_size; 47 48 uint32_t nr_cores; 49 uint64_t cores_mask; 50 } PnvChip; 51 52 typedef struct PnvChipClass { 53 /*< private >*/ 54 SysBusDeviceClass parent_class; 55 56 /*< public >*/ 57 const char *cpu_model; 58 PnvChipType chip_type; 59 uint64_t chip_cfam_id; 60 uint64_t cores_mask; 61 62 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 63 } PnvChipClass; 64 65 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" 66 #define PNV_CHIP_POWER8E(obj) \ 67 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 68 69 #define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8" 70 #define PNV_CHIP_POWER8(obj) \ 71 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 72 73 #define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL" 74 #define PNV_CHIP_POWER8NVL(obj) \ 75 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 76 77 #define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9" 78 #define PNV_CHIP_POWER9(obj) \ 79 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 80 81 /* 82 * This generates a HW chip id depending on an index: 83 * 84 * 0x0, 0x1, 0x10, 0x11 85 * 86 * 4 chips should be the maximum 87 */ 88 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 89 90 #define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") 91 #define POWERNV_MACHINE(obj) \ 92 OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) 93 94 typedef struct PnvMachineState { 95 /*< private >*/ 96 MachineState parent_obj; 97 98 uint32_t initrd_base; 99 long initrd_size; 100 101 uint32_t num_chips; 102 PnvChip **chips; 103 } PnvMachineState; 104 105 #define PNV_FDT_ADDR 0x01000000 106 107 #endif /* _PPC_PNV_H */ 108