1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef _PPC_PNV_H 20 #define _PPC_PNV_H 21 22 #include "hw/boards.h" 23 #include "hw/sysbus.h" 24 #include "hw/ppc/pnv_lpc.h" 25 #include "hw/ppc/pnv_psi.h" 26 27 #define TYPE_PNV_CHIP "powernv-chip" 28 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 29 #define PNV_CHIP_CLASS(klass) \ 30 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 31 #define PNV_CHIP_GET_CLASS(obj) \ 32 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 33 34 typedef enum PnvChipType { 35 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 36 PNV_CHIP_POWER8, /* AKA Venice */ 37 PNV_CHIP_POWER8NVL, /* AKA Naples */ 38 PNV_CHIP_POWER9, /* AKA Nimbus */ 39 } PnvChipType; 40 41 typedef struct PnvChip { 42 /*< private >*/ 43 SysBusDevice parent_obj; 44 45 /*< public >*/ 46 uint32_t chip_id; 47 uint64_t ram_start; 48 uint64_t ram_size; 49 50 uint32_t nr_cores; 51 uint64_t cores_mask; 52 void *cores; 53 54 hwaddr xscom_base; 55 MemoryRegion xscom_mmio; 56 MemoryRegion xscom; 57 AddressSpace xscom_as; 58 MemoryRegion icp_mmio; 59 60 PnvLpcController lpc; 61 PnvPsi psi; 62 } PnvChip; 63 64 typedef struct PnvChipClass { 65 /*< private >*/ 66 SysBusDeviceClass parent_class; 67 68 /*< public >*/ 69 const char *cpu_model; 70 PnvChipType chip_type; 71 uint64_t chip_cfam_id; 72 uint64_t cores_mask; 73 74 hwaddr xscom_base; 75 hwaddr xscom_core_base; 76 77 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 78 } PnvChipClass; 79 80 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" 81 #define PNV_CHIP_POWER8E(obj) \ 82 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 83 84 #define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8" 85 #define PNV_CHIP_POWER8(obj) \ 86 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 87 88 #define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL" 89 #define PNV_CHIP_POWER8NVL(obj) \ 90 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 91 92 #define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9" 93 #define PNV_CHIP_POWER9(obj) \ 94 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 95 96 /* 97 * This generates a HW chip id depending on an index, as found on a 98 * two socket system with dual chip modules : 99 * 100 * 0x0, 0x1, 0x10, 0x11 101 * 102 * 4 chips should be the maximum 103 * 104 * TODO: use a machine property to define the chip ids 105 */ 106 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 107 108 /* 109 * Converts back a HW chip id to an index. This is useful to calculate 110 * the MMIO addresses of some controllers which depend on the chip id. 111 */ 112 #define PNV_CHIP_INDEX(chip) \ 113 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 114 115 #define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") 116 #define POWERNV_MACHINE(obj) \ 117 OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) 118 119 typedef struct PnvMachineState { 120 /*< private >*/ 121 MachineState parent_obj; 122 123 uint32_t initrd_base; 124 long initrd_size; 125 126 uint32_t num_chips; 127 PnvChip **chips; 128 129 ISABus *isa_bus; 130 uint32_t cpld_irqstate; 131 } PnvMachineState; 132 133 #define PNV_FDT_ADDR 0x01000000 134 #define PNV_TIMEBASE_FREQ 512000000ULL 135 136 /* 137 * POWER8 MMIO base addresses 138 */ 139 #define PNV_XSCOM_SIZE 0x800000000ull 140 #define PNV_XSCOM_BASE(chip) \ 141 (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 142 143 /* 144 * XSCOM 0x20109CA defines the ICP BAR: 145 * 146 * 0:29 : bits 14 to 43 of address to define 1 MB region. 147 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 148 * 31:63 : Constant 0 149 * 150 * Usually defined as : 151 * 152 * 0xffffe00200000000 -> 0x0003ffff80000000 153 * 0xffffe00600000000 -> 0x0003ffff80100000 154 * 0xffffe02200000000 -> 0x0003ffff80800000 155 * 0xffffe02600000000 -> 0x0003ffff80900000 156 */ 157 #define PNV_ICP_SIZE 0x0000000000100000ull 158 #define PNV_ICP_BASE(chip) \ 159 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 160 161 162 #define PNV_PSIHB_SIZE 0x0000000000100000ull 163 #define PNV_PSIHB_BASE(chip) \ 164 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 165 166 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 167 #define PNV_PSIHB_FSP_BASE(chip) \ 168 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 169 PNV_PSIHB_FSP_SIZE) 170 171 #endif /* _PPC_PNV_H */ 172