1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef _PPC_PNV_H 20 #define _PPC_PNV_H 21 22 #include "hw/boards.h" 23 #include "hw/sysbus.h" 24 #include "hw/ipmi/ipmi.h" 25 #include "hw/ppc/pnv_lpc.h" 26 #include "hw/ppc/pnv_psi.h" 27 #include "hw/ppc/pnv_occ.h" 28 #include "hw/ppc/pnv_xive.h" 29 30 #define TYPE_PNV_CHIP "pnv-chip" 31 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 32 #define PNV_CHIP_CLASS(klass) \ 33 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 34 #define PNV_CHIP_GET_CLASS(obj) \ 35 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 36 37 typedef enum PnvChipType { 38 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 39 PNV_CHIP_POWER8, /* AKA Venice */ 40 PNV_CHIP_POWER8NVL, /* AKA Naples */ 41 PNV_CHIP_POWER9, /* AKA Nimbus */ 42 } PnvChipType; 43 44 typedef struct PnvChip { 45 /*< private >*/ 46 SysBusDevice parent_obj; 47 48 /*< public >*/ 49 uint32_t chip_id; 50 uint64_t ram_start; 51 uint64_t ram_size; 52 53 uint32_t nr_cores; 54 uint64_t cores_mask; 55 void *cores; 56 57 hwaddr xscom_base; 58 MemoryRegion xscom_mmio; 59 MemoryRegion xscom; 60 AddressSpace xscom_as; 61 } PnvChip; 62 63 #define TYPE_PNV8_CHIP "pnv8-chip" 64 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 65 66 typedef struct Pnv8Chip { 67 /*< private >*/ 68 PnvChip parent_obj; 69 70 /*< public >*/ 71 MemoryRegion icp_mmio; 72 73 PnvLpcController lpc; 74 PnvPsi psi; 75 PnvOCC occ; 76 } Pnv8Chip; 77 78 #define TYPE_PNV9_CHIP "pnv9-chip" 79 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 80 81 typedef struct Pnv9Chip { 82 /*< private >*/ 83 PnvChip parent_obj; 84 85 /*< public >*/ 86 PnvXive xive; 87 } Pnv9Chip; 88 89 typedef struct PnvChipClass { 90 /*< private >*/ 91 SysBusDeviceClass parent_class; 92 93 /*< public >*/ 94 PnvChipType chip_type; 95 uint64_t chip_cfam_id; 96 uint64_t cores_mask; 97 98 hwaddr xscom_base; 99 100 DeviceRealize parent_realize; 101 102 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 103 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 104 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 105 } PnvChipClass; 106 107 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 108 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 109 110 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 111 #define PNV_CHIP_POWER8E(obj) \ 112 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 113 114 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 115 #define PNV_CHIP_POWER8(obj) \ 116 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 117 118 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 119 #define PNV_CHIP_POWER8NVL(obj) \ 120 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 121 122 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 123 #define PNV_CHIP_POWER9(obj) \ 124 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 125 126 /* 127 * This generates a HW chip id depending on an index, as found on a 128 * two socket system with dual chip modules : 129 * 130 * 0x0, 0x1, 0x10, 0x11 131 * 132 * 4 chips should be the maximum 133 * 134 * TODO: use a machine property to define the chip ids 135 */ 136 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 137 138 /* 139 * Converts back a HW chip id to an index. This is useful to calculate 140 * the MMIO addresses of some controllers which depend on the chip id. 141 */ 142 #define PNV_CHIP_INDEX(chip) \ 143 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 144 145 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 146 #define PNV_MACHINE(obj) \ 147 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 148 149 typedef struct PnvMachineState { 150 /*< private >*/ 151 MachineState parent_obj; 152 153 uint32_t initrd_base; 154 long initrd_size; 155 156 uint32_t num_chips; 157 PnvChip **chips; 158 159 ISABus *isa_bus; 160 uint32_t cpld_irqstate; 161 162 IPMIBmc *bmc; 163 Notifier powerdown_notifier; 164 } PnvMachineState; 165 166 static inline bool pnv_chip_is_power9(const PnvChip *chip) 167 { 168 return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; 169 } 170 171 static inline bool pnv_is_power9(PnvMachineState *pnv) 172 { 173 return pnv_chip_is_power9(pnv->chips[0]); 174 } 175 176 #define PNV_FDT_ADDR 0x01000000 177 #define PNV_TIMEBASE_FREQ 512000000ULL 178 179 /* 180 * BMC helpers 181 */ 182 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 183 void pnv_bmc_powerdown(IPMIBmc *bmc); 184 185 /* 186 * POWER8 MMIO base addresses 187 */ 188 #define PNV_XSCOM_SIZE 0x800000000ull 189 #define PNV_XSCOM_BASE(chip) \ 190 (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 191 192 /* 193 * XSCOM 0x20109CA defines the ICP BAR: 194 * 195 * 0:29 : bits 14 to 43 of address to define 1 MB region. 196 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 197 * 31:63 : Constant 0 198 * 199 * Usually defined as : 200 * 201 * 0xffffe00200000000 -> 0x0003ffff80000000 202 * 0xffffe00600000000 -> 0x0003ffff80100000 203 * 0xffffe02200000000 -> 0x0003ffff80800000 204 * 0xffffe02600000000 -> 0x0003ffff80900000 205 */ 206 #define PNV_ICP_SIZE 0x0000000000100000ull 207 #define PNV_ICP_BASE(chip) \ 208 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 209 210 211 #define PNV_PSIHB_SIZE 0x0000000000100000ull 212 #define PNV_PSIHB_BASE(chip) \ 213 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 214 215 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 216 #define PNV_PSIHB_FSP_BASE(chip) \ 217 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 218 PNV_PSIHB_FSP_SIZE) 219 220 /* 221 * POWER9 MMIO base addresses 222 */ 223 #define PNV9_CHIP_BASE(chip, base) \ 224 ((base) + ((uint64_t) (chip)->chip_id << 42)) 225 226 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 227 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 228 229 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 230 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 231 232 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 233 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 234 235 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 236 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 237 238 239 #endif /* _PPC_PNV_H */ 240