1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 34 #define TYPE_PNV_CHIP "pnv-chip" 35 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 36 #define PNV_CHIP_CLASS(klass) \ 37 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 38 #define PNV_CHIP_GET_CLASS(obj) \ 39 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 40 41 typedef enum PnvChipType { 42 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 43 PNV_CHIP_POWER8, /* AKA Venice */ 44 PNV_CHIP_POWER8NVL, /* AKA Naples */ 45 PNV_CHIP_POWER9, /* AKA Nimbus */ 46 } PnvChipType; 47 48 typedef struct PnvChip { 49 /*< private >*/ 50 SysBusDevice parent_obj; 51 52 /*< public >*/ 53 uint32_t chip_id; 54 uint64_t ram_start; 55 uint64_t ram_size; 56 57 uint32_t nr_cores; 58 uint64_t cores_mask; 59 PnvCore **cores; 60 61 MemoryRegion xscom_mmio; 62 MemoryRegion xscom; 63 AddressSpace xscom_as; 64 65 gchar *dt_isa_nodename; 66 } PnvChip; 67 68 #define TYPE_PNV8_CHIP "pnv8-chip" 69 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 70 71 typedef struct Pnv8Chip { 72 /*< private >*/ 73 PnvChip parent_obj; 74 75 /*< public >*/ 76 MemoryRegion icp_mmio; 77 78 PnvLpcController lpc; 79 Pnv8Psi psi; 80 PnvOCC occ; 81 PnvHomer homer; 82 } Pnv8Chip; 83 84 #define TYPE_PNV9_CHIP "pnv9-chip" 85 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 86 87 typedef struct Pnv9Chip { 88 /*< private >*/ 89 PnvChip parent_obj; 90 91 /*< public >*/ 92 PnvXive xive; 93 Pnv9Psi psi; 94 PnvLpcController lpc; 95 PnvOCC occ; 96 PnvHomer homer; 97 98 uint32_t nr_quads; 99 PnvQuad *quads; 100 } Pnv9Chip; 101 102 /* 103 * A SMT8 fused core is a pair of SMT4 cores. 104 */ 105 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 106 107 typedef struct PnvChipClass { 108 /*< private >*/ 109 SysBusDeviceClass parent_class; 110 111 /*< public >*/ 112 PnvChipType chip_type; 113 uint64_t chip_cfam_id; 114 uint64_t cores_mask; 115 116 DeviceRealize parent_realize; 117 118 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 119 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 120 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 121 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 122 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 123 void (*dt_populate)(PnvChip *chip, void *fdt); 124 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 125 } PnvChipClass; 126 127 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 128 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 129 130 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 131 #define PNV_CHIP_POWER8E(obj) \ 132 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 133 134 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 135 #define PNV_CHIP_POWER8(obj) \ 136 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 137 138 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 139 #define PNV_CHIP_POWER8NVL(obj) \ 140 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 141 142 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 143 #define PNV_CHIP_POWER9(obj) \ 144 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 145 146 /* 147 * This generates a HW chip id depending on an index, as found on a 148 * two socket system with dual chip modules : 149 * 150 * 0x0, 0x1, 0x10, 0x11 151 * 152 * 4 chips should be the maximum 153 * 154 * TODO: use a machine property to define the chip ids 155 */ 156 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 157 158 /* 159 * Converts back a HW chip id to an index. This is useful to calculate 160 * the MMIO addresses of some controllers which depend on the chip id. 161 */ 162 #define PNV_CHIP_INDEX(chip) \ 163 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 164 165 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 166 167 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 168 #define PNV_MACHINE(obj) \ 169 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 170 171 typedef struct PnvMachineState { 172 /*< private >*/ 173 MachineState parent_obj; 174 175 uint32_t initrd_base; 176 long initrd_size; 177 178 uint32_t num_chips; 179 PnvChip **chips; 180 181 ISABus *isa_bus; 182 uint32_t cpld_irqstate; 183 184 IPMIBmc *bmc; 185 Notifier powerdown_notifier; 186 187 PnvPnor *pnor; 188 } PnvMachineState; 189 190 static inline bool pnv_chip_is_power9(const PnvChip *chip) 191 { 192 return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; 193 } 194 195 static inline bool pnv_is_power9(PnvMachineState *pnv) 196 { 197 return pnv_chip_is_power9(pnv->chips[0]); 198 } 199 200 #define PNV_FDT_ADDR 0x01000000 201 #define PNV_TIMEBASE_FREQ 512000000ULL 202 203 /* 204 * BMC helpers 205 */ 206 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 207 void pnv_bmc_powerdown(IPMIBmc *bmc); 208 IPMIBmc *pnv_bmc_create(void); 209 210 /* 211 * POWER8 MMIO base addresses 212 */ 213 #define PNV_XSCOM_SIZE 0x800000000ull 214 #define PNV_XSCOM_BASE(chip) \ 215 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 216 217 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull 218 #define PNV_OCC_COMMON_AREA(chip) \ 219 (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ 220 PNV_OCC_COMMON_AREA_SIZE)) 221 222 #define PNV_HOMER_SIZE 0x0000000000300000ull 223 #define PNV_HOMER_BASE(chip) \ 224 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 225 226 227 /* 228 * XSCOM 0x20109CA defines the ICP BAR: 229 * 230 * 0:29 : bits 14 to 43 of address to define 1 MB region. 231 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 232 * 31:63 : Constant 0 233 * 234 * Usually defined as : 235 * 236 * 0xffffe00200000000 -> 0x0003ffff80000000 237 * 0xffffe00600000000 -> 0x0003ffff80100000 238 * 0xffffe02200000000 -> 0x0003ffff80800000 239 * 0xffffe02600000000 -> 0x0003ffff80900000 240 */ 241 #define PNV_ICP_SIZE 0x0000000000100000ull 242 #define PNV_ICP_BASE(chip) \ 243 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 244 245 246 #define PNV_PSIHB_SIZE 0x0000000000100000ull 247 #define PNV_PSIHB_BASE(chip) \ 248 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 249 250 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 251 #define PNV_PSIHB_FSP_BASE(chip) \ 252 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 253 PNV_PSIHB_FSP_SIZE) 254 255 /* 256 * POWER9 MMIO base addresses 257 */ 258 #define PNV9_CHIP_BASE(chip, base) \ 259 ((base) + ((uint64_t) (chip)->chip_id << 42)) 260 261 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 262 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 263 264 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 265 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 266 267 #define PNV9_LPCM_SIZE 0x0000000100000000ull 268 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 269 270 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 271 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 272 273 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 274 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 275 276 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 277 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 278 279 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 280 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 281 282 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 283 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 284 285 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull 286 #define PNV9_OCC_COMMON_AREA(chip) \ 287 (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ 288 PNV9_OCC_COMMON_AREA_SIZE)) 289 290 #define PNV9_HOMER_SIZE 0x0000000000300000ull 291 #define PNV9_HOMER_BASE(chip) \ 292 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 293 #endif /* PPC_PNV_H */ 294