1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_sbe.h" 31 #include "hw/ppc/pnv_homer.h" 32 #include "hw/ppc/pnv_xive.h" 33 #include "hw/ppc/pnv_core.h" 34 #include "hw/pci-host/pnv_phb3.h" 35 #include "hw/pci-host/pnv_phb4.h" 36 #include "qom/object.h" 37 38 #define TYPE_PNV_CHIP "pnv-chip" 39 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 40 PNV_CHIP) 41 42 struct PnvChip { 43 /*< private >*/ 44 SysBusDevice parent_obj; 45 46 /*< public >*/ 47 uint32_t chip_id; 48 uint64_t ram_start; 49 uint64_t ram_size; 50 51 uint32_t nr_cores; 52 uint32_t nr_threads; 53 uint64_t cores_mask; 54 PnvCore **cores; 55 56 uint32_t num_pecs; 57 58 MemoryRegion xscom_mmio; 59 MemoryRegion xscom; 60 AddressSpace xscom_as; 61 62 MemoryRegion *fw_mr; 63 gchar *dt_isa_nodename; 64 }; 65 66 #define TYPE_PNV8_CHIP "pnv8-chip" 67 typedef struct Pnv8Chip Pnv8Chip; 68 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 69 TYPE_PNV8_CHIP) 70 71 struct Pnv8Chip { 72 /*< private >*/ 73 PnvChip parent_obj; 74 75 /*< public >*/ 76 MemoryRegion icp_mmio; 77 78 PnvLpcController lpc; 79 Pnv8Psi psi; 80 PnvOCC occ; 81 PnvHomer homer; 82 83 #define PNV8_CHIP_PHB3_MAX 4 84 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; 85 uint32_t num_phbs; 86 87 XICSFabric *xics; 88 }; 89 90 #define TYPE_PNV9_CHIP "pnv9-chip" 91 typedef struct Pnv9Chip Pnv9Chip; 92 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 93 TYPE_PNV9_CHIP) 94 95 struct Pnv9Chip { 96 /*< private >*/ 97 PnvChip parent_obj; 98 99 /*< public >*/ 100 PnvXive xive; 101 Pnv9Psi psi; 102 PnvLpcController lpc; 103 PnvOCC occ; 104 PnvSBE sbe; 105 PnvHomer homer; 106 107 uint32_t nr_quads; 108 PnvQuad *quads; 109 110 #define PNV9_CHIP_MAX_PEC 3 111 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 112 }; 113 114 /* 115 * A SMT8 fused core is a pair of SMT4 cores. 116 */ 117 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 118 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 119 120 #define TYPE_PNV10_CHIP "pnv10-chip" 121 typedef struct Pnv10Chip Pnv10Chip; 122 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 123 TYPE_PNV10_CHIP) 124 125 struct Pnv10Chip { 126 /*< private >*/ 127 PnvChip parent_obj; 128 129 /*< public >*/ 130 PnvXive2 xive; 131 Pnv9Psi psi; 132 PnvLpcController lpc; 133 PnvOCC occ; 134 PnvSBE sbe; 135 PnvHomer homer; 136 137 uint32_t nr_quads; 138 PnvQuad *quads; 139 140 #define PNV10_CHIP_MAX_PEC 2 141 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; 142 }; 143 144 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 145 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 146 147 struct PnvChipClass { 148 /*< private >*/ 149 SysBusDeviceClass parent_class; 150 151 /*< public >*/ 152 uint64_t chip_cfam_id; 153 uint64_t cores_mask; 154 uint32_t num_pecs; 155 uint32_t num_phbs; 156 157 DeviceRealize parent_realize; 158 159 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 160 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 161 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 162 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 163 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 164 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 165 void (*dt_populate)(PnvChip *chip, void *fdt); 166 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 167 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 168 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 169 }; 170 171 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 172 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 173 174 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 175 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E, 176 TYPE_PNV_CHIP_POWER8E) 177 178 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 179 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, 180 TYPE_PNV_CHIP_POWER8) 181 182 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 183 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, 184 TYPE_PNV_CHIP_POWER8NVL) 185 186 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 187 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, 188 TYPE_PNV_CHIP_POWER9) 189 190 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0") 191 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, 192 TYPE_PNV_CHIP_POWER10) 193 194 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 195 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, 196 int index, int chip_id); 197 198 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 199 typedef struct PnvMachineClass PnvMachineClass; 200 typedef struct PnvMachineState PnvMachineState; 201 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass, 202 PNV_MACHINE, TYPE_PNV_MACHINE) 203 204 205 struct PnvMachineClass { 206 /*< private >*/ 207 MachineClass parent_class; 208 209 /*< public >*/ 210 const char *compat; 211 int compat_size; 212 213 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 214 }; 215 216 struct PnvMachineState { 217 /*< private >*/ 218 MachineState parent_obj; 219 220 uint32_t initrd_base; 221 long initrd_size; 222 223 uint32_t num_chips; 224 PnvChip **chips; 225 226 ISABus *isa_bus; 227 uint32_t cpld_irqstate; 228 229 IPMIBmc *bmc; 230 Notifier powerdown_notifier; 231 232 PnvPnor *pnor; 233 234 hwaddr fw_load_addr; 235 }; 236 237 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id); 238 239 #define PNV_FDT_ADDR 0x01000000 240 #define PNV_TIMEBASE_FREQ 512000000ULL 241 242 /* 243 * BMC helpers 244 */ 245 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 246 void pnv_bmc_powerdown(IPMIBmc *bmc); 247 IPMIBmc *pnv_bmc_create(PnvPnor *pnor); 248 IPMIBmc *pnv_bmc_find(Error **errp); 249 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); 250 251 /* 252 * POWER8 MMIO base addresses 253 */ 254 #define PNV_XSCOM_SIZE 0x800000000ull 255 #define PNV_XSCOM_BASE(chip) \ 256 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 257 258 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 259 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 260 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 261 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 262 263 #define PNV_HOMER_SIZE 0x0000000000400000ull 264 #define PNV_HOMER_BASE(chip) \ 265 (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) 266 267 268 /* 269 * XSCOM 0x20109CA defines the ICP BAR: 270 * 271 * 0:29 : bits 14 to 43 of address to define 1 MB region. 272 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 273 * 31:63 : Constant 0 274 * 275 * Usually defined as : 276 * 277 * 0xffffe00200000000 -> 0x0003ffff80000000 278 * 0xffffe00600000000 -> 0x0003ffff80100000 279 * 0xffffe02200000000 -> 0x0003ffff80800000 280 * 0xffffe02600000000 -> 0x0003ffff80900000 281 */ 282 #define PNV_ICP_SIZE 0x0000000000100000ull 283 #define PNV_ICP_BASE(chip) \ 284 (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE) 285 286 287 #define PNV_PSIHB_SIZE 0x0000000000100000ull 288 #define PNV_PSIHB_BASE(chip) \ 289 (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE) 290 291 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 292 #define PNV_PSIHB_FSP_BASE(chip) \ 293 (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \ 294 PNV_PSIHB_FSP_SIZE) 295 296 /* 297 * POWER9 MMIO base addresses 298 */ 299 #define PNV9_CHIP_BASE(chip, base) \ 300 ((base) + ((uint64_t) (chip)->chip_id << 42)) 301 302 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 303 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 304 305 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 306 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 307 308 #define PNV9_LPCM_SIZE 0x0000000100000000ull 309 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 310 311 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 312 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 313 314 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 315 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 316 317 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 318 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 319 320 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 321 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 322 323 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 324 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 325 326 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 327 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 328 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 329 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 330 331 #define PNV9_HOMER_SIZE 0x0000000000400000ull 332 #define PNV9_HOMER_BASE(chip) \ 333 (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE) 334 335 /* 336 * POWER10 MMIO base addresses - 16TB stride per chip 337 */ 338 #define PNV10_CHIP_BASE(chip, base) \ 339 ((base) + ((uint64_t) (chip)->chip_id << 44)) 340 341 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 342 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 343 344 #define PNV10_LPCM_SIZE 0x0000000100000000ull 345 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 346 347 #define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull 348 #define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull) 349 350 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 351 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 352 353 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 354 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 355 356 #define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull 357 #define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull) 358 359 #define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull 360 #define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull) 361 362 #define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull 363 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull) 364 365 #define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull 366 #define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull) 367 368 #define PNV10_XIVE2_END_SIZE 0x0000020000000000ull 369 #define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull) 370 371 #define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 372 #define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull 373 #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \ 374 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 375 376 #define PNV10_HOMER_SIZE 0x0000000000400000ull 377 #define PNV10_HOMER_BASE(chip) \ 378 (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE) 379 380 #endif /* PPC_PNV_H */ 381