1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 #include "qapi/error.h" 10 11 /* PCI includes legacy ISA access. */ 12 #include "hw/isa/isa.h" 13 14 #include "hw/pci/pcie.h" 15 16 /* PCI bus */ 17 18 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_SLOT_MAX 32 22 #define PCI_FUNC_MAX 8 23 24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 25 #include "hw/pci/pci_ids.h" 26 27 /* QEMU-specific Vendor and Device ID definitions */ 28 29 /* IBM (0x1014) */ 30 #define PCI_DEVICE_ID_IBM_440GX 0x027f 31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 32 33 /* Hitachi (0x1054) */ 34 #define PCI_VENDOR_ID_HITACHI 0x1054 35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 36 37 /* Apple (0x106b) */ 38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 43 44 /* Realtek (0x10ec) */ 45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 46 47 /* Xilinx (0x10ee) */ 48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 49 50 /* Marvell (0x11ab) */ 51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 52 53 /* QEMU/Bochs VGA (0x1234) */ 54 #define PCI_VENDOR_ID_QEMU 0x1234 55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 56 57 /* VMWare (0x15ad) */ 58 #define PCI_VENDOR_ID_VMWARE 0x15ad 59 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 60 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 61 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 62 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 63 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 64 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 65 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 66 67 /* Intel (0x8086) */ 68 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 69 #define PCI_DEVICE_ID_INTEL_82557 0x1229 70 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 71 72 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 73 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBDEVICE_ID_QEMU 0x1100 76 77 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 78 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 79 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 80 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 81 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 82 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 83 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 84 85 #define PCI_VENDOR_ID_REDHAT 0x1b36 86 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 87 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 88 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 89 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 90 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 91 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 92 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 93 94 #define FMT_PCIBUS PRIx64 95 96 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 97 uint32_t address, uint32_t data, int len); 98 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 99 uint32_t address, int len); 100 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 101 pcibus_t addr, pcibus_t size, int type); 102 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 103 104 typedef struct PCIIORegion { 105 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 106 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 107 pcibus_t size; 108 uint8_t type; 109 MemoryRegion *memory; 110 MemoryRegion *address_space; 111 } PCIIORegion; 112 113 #define PCI_ROM_SLOT 6 114 #define PCI_NUM_REGIONS 7 115 116 enum { 117 QEMU_PCI_VGA_MEM, 118 QEMU_PCI_VGA_IO_LO, 119 QEMU_PCI_VGA_IO_HI, 120 QEMU_PCI_VGA_NUM_REGIONS, 121 }; 122 123 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 124 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 125 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 126 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 127 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 128 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 129 130 #include "hw/pci/pci_regs.h" 131 132 /* PCI HEADER_TYPE */ 133 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 134 135 /* Size of the standard PCI config header */ 136 #define PCI_CONFIG_HEADER_SIZE 0x40 137 /* Size of the standard PCI config space */ 138 #define PCI_CONFIG_SPACE_SIZE 0x100 139 /* Size of the standart PCIe config space: 4KB */ 140 #define PCIE_CONFIG_SPACE_SIZE 0x1000 141 142 #define PCI_NUM_PINS 4 /* A-D */ 143 144 /* Bits in cap_present field. */ 145 enum { 146 QEMU_PCI_CAP_MSI = 0x1, 147 QEMU_PCI_CAP_MSIX = 0x2, 148 QEMU_PCI_CAP_EXPRESS = 0x4, 149 150 /* multifunction capable device */ 151 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 152 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 153 154 /* command register SERR bit enabled */ 155 #define QEMU_PCI_CAP_SERR_BITNR 4 156 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 157 /* Standard hot plug controller. */ 158 #define QEMU_PCI_SHPC_BITNR 5 159 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 160 #define QEMU_PCI_SLOTID_BITNR 6 161 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 162 /* PCI Express capability - Power Controller Present */ 163 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 164 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 165 }; 166 167 #define TYPE_PCI_DEVICE "pci-device" 168 #define PCI_DEVICE(obj) \ 169 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 170 #define PCI_DEVICE_CLASS(klass) \ 171 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 172 #define PCI_DEVICE_GET_CLASS(obj) \ 173 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 174 175 typedef struct PCIINTxRoute { 176 enum { 177 PCI_INTX_ENABLED, 178 PCI_INTX_INVERTED, 179 PCI_INTX_DISABLED, 180 } mode; 181 int irq; 182 } PCIINTxRoute; 183 184 typedef struct PCIDeviceClass { 185 DeviceClass parent_class; 186 187 int (*init)(PCIDevice *dev); 188 PCIUnregisterFunc *exit; 189 PCIConfigReadFunc *config_read; 190 PCIConfigWriteFunc *config_write; 191 192 uint16_t vendor_id; 193 uint16_t device_id; 194 uint8_t revision; 195 uint16_t class_id; 196 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 197 uint16_t subsystem_id; /* only for header type = 0 */ 198 199 /* 200 * pci-to-pci bridge or normal device. 201 * This doesn't mean pci host switch. 202 * When card bus bridge is supported, this would be enhanced. 203 */ 204 int is_bridge; 205 206 /* pcie stuff */ 207 int is_express; /* is this device pci express? */ 208 209 /* rom bar */ 210 const char *romfile; 211 } PCIDeviceClass; 212 213 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 214 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 215 MSIMessage msg); 216 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 217 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 218 unsigned int vector_start, 219 unsigned int vector_end); 220 221 struct PCIDevice { 222 DeviceState qdev; 223 224 /* PCI config space */ 225 uint8_t *config; 226 227 /* Used to enable config checks on load. Note that writable bits are 228 * never checked even if set in cmask. */ 229 uint8_t *cmask; 230 231 /* Used to implement R/W bytes */ 232 uint8_t *wmask; 233 234 /* Used to implement RW1C(Write 1 to Clear) bytes */ 235 uint8_t *w1cmask; 236 237 /* Used to allocate config space for capabilities. */ 238 uint8_t *used; 239 240 /* the following fields are read only */ 241 PCIBus *bus; 242 int32_t devfn; 243 char name[64]; 244 PCIIORegion io_regions[PCI_NUM_REGIONS]; 245 AddressSpace bus_master_as; 246 MemoryRegion bus_master_enable_region; 247 248 /* do not access the following fields */ 249 PCIConfigReadFunc *config_read; 250 PCIConfigWriteFunc *config_write; 251 252 /* Legacy PCI VGA regions */ 253 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 254 bool has_vga; 255 256 /* Current IRQ levels. Used internally by the generic PCI code. */ 257 uint8_t irq_state; 258 259 /* Capability bits */ 260 uint32_t cap_present; 261 262 /* Offset of MSI-X capability in config space */ 263 uint8_t msix_cap; 264 265 /* MSI-X entries */ 266 int msix_entries_nr; 267 268 /* Space to store MSIX table & pending bit array */ 269 uint8_t *msix_table; 270 uint8_t *msix_pba; 271 /* MemoryRegion container for msix exclusive BAR setup */ 272 MemoryRegion msix_exclusive_bar; 273 /* Memory Regions for MSIX table and pending bit entries. */ 274 MemoryRegion msix_table_mmio; 275 MemoryRegion msix_pba_mmio; 276 /* Reference-count for entries actually in use by driver. */ 277 unsigned *msix_entry_used; 278 /* MSIX function mask set or MSIX disabled */ 279 bool msix_function_masked; 280 /* Version id needed for VMState */ 281 int32_t version_id; 282 283 /* Offset of MSI capability in config space */ 284 uint8_t msi_cap; 285 286 /* PCI Express */ 287 PCIExpressDevice exp; 288 289 /* SHPC */ 290 SHPCDevice *shpc; 291 292 /* Location of option rom */ 293 char *romfile; 294 bool has_rom; 295 MemoryRegion rom; 296 uint32_t rom_bar; 297 298 /* INTx routing notifier */ 299 PCIINTxRoutingNotifier intx_routing_notifier; 300 301 /* MSI-X notifiers */ 302 MSIVectorUseNotifier msix_vector_use_notifier; 303 MSIVectorReleaseNotifier msix_vector_release_notifier; 304 MSIVectorPollNotifier msix_vector_poll_notifier; 305 }; 306 307 void pci_register_bar(PCIDevice *pci_dev, int region_num, 308 uint8_t attr, MemoryRegion *memory); 309 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 310 MemoryRegion *io_lo, MemoryRegion *io_hi); 311 void pci_unregister_vga(PCIDevice *pci_dev); 312 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 313 314 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 315 uint8_t offset, uint8_t size); 316 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 317 uint8_t offset, uint8_t size, 318 Error **errp); 319 320 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 321 322 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 323 324 325 uint32_t pci_default_read_config(PCIDevice *d, 326 uint32_t address, int len); 327 void pci_default_write_config(PCIDevice *d, 328 uint32_t address, uint32_t val, int len); 329 void pci_device_save(PCIDevice *s, QEMUFile *f); 330 int pci_device_load(PCIDevice *s, QEMUFile *f); 331 MemoryRegion *pci_address_space(PCIDevice *dev); 332 MemoryRegion *pci_address_space_io(PCIDevice *dev); 333 334 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 335 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 336 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 337 338 #define TYPE_PCI_BUS "PCI" 339 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 340 #define TYPE_PCIE_BUS "PCIE" 341 342 bool pci_bus_is_express(PCIBus *bus); 343 bool pci_bus_is_root(PCIBus *bus); 344 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 345 const char *name, 346 MemoryRegion *address_space_mem, 347 MemoryRegion *address_space_io, 348 uint8_t devfn_min, const char *typename); 349 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 350 MemoryRegion *address_space_mem, 351 MemoryRegion *address_space_io, 352 uint8_t devfn_min, const char *typename); 353 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 354 void *irq_opaque, int nirq); 355 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 356 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 357 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 358 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 359 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 360 void *irq_opaque, 361 MemoryRegion *address_space_mem, 362 MemoryRegion *address_space_io, 363 uint8_t devfn_min, int nirq, const char *typename); 364 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 365 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 366 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 367 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 368 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 369 PCIINTxRoutingNotifier notifier); 370 void pci_device_reset(PCIDevice *dev); 371 372 PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, 373 const char *default_model, 374 const char *default_devaddr); 375 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 376 const char *default_model, 377 const char *default_devaddr); 378 379 PCIDevice *pci_vga_init(PCIBus *bus); 380 381 int pci_bus_num(PCIBus *s); 382 void pci_for_each_device(PCIBus *bus, int bus_num, 383 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 384 void *opaque); 385 void pci_for_each_bus_depth_first(PCIBus *bus, 386 void *(*begin)(PCIBus *bus, void *parent_state), 387 void (*end)(PCIBus *bus, void *state), 388 void *parent_state); 389 390 /* Use this wrapper when specific scan order is not required. */ 391 static inline 392 void pci_for_each_bus(PCIBus *bus, 393 void (*fn)(PCIBus *bus, void *opaque), 394 void *opaque) 395 { 396 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 397 } 398 399 PCIBus *pci_find_primary_bus(void); 400 PCIBus *pci_device_root_bus(const PCIDevice *d); 401 const char *pci_root_bus_path(PCIDevice *dev); 402 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 403 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 404 PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr); 405 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 406 407 int pci_parse_devaddr(const char *addr, int *domp, int *busp, 408 unsigned int *slotp, unsigned int *funcp); 409 410 void pci_device_deassert_intx(PCIDevice *dev); 411 412 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 413 414 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 415 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 416 417 static inline void 418 pci_set_byte(uint8_t *config, uint8_t val) 419 { 420 *config = val; 421 } 422 423 static inline uint8_t 424 pci_get_byte(const uint8_t *config) 425 { 426 return *config; 427 } 428 429 static inline void 430 pci_set_word(uint8_t *config, uint16_t val) 431 { 432 stw_le_p(config, val); 433 } 434 435 static inline uint16_t 436 pci_get_word(const uint8_t *config) 437 { 438 return lduw_le_p(config); 439 } 440 441 static inline void 442 pci_set_long(uint8_t *config, uint32_t val) 443 { 444 stl_le_p(config, val); 445 } 446 447 static inline uint32_t 448 pci_get_long(const uint8_t *config) 449 { 450 return ldl_le_p(config); 451 } 452 453 static inline void 454 pci_set_quad(uint8_t *config, uint64_t val) 455 { 456 cpu_to_le64w((uint64_t *)config, val); 457 } 458 459 static inline uint64_t 460 pci_get_quad(const uint8_t *config) 461 { 462 return le64_to_cpup((const uint64_t *)config); 463 } 464 465 static inline void 466 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 467 { 468 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 469 } 470 471 static inline void 472 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 473 { 474 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 475 } 476 477 static inline void 478 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 479 { 480 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 481 } 482 483 static inline void 484 pci_config_set_class(uint8_t *pci_config, uint16_t val) 485 { 486 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 487 } 488 489 static inline void 490 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 491 { 492 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 493 } 494 495 static inline void 496 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 497 { 498 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 499 } 500 501 /* 502 * helper functions to do bit mask operation on configuration space. 503 * Just to set bit, use test-and-set and discard returned value. 504 * Just to clear bit, use test-and-clear and discard returned value. 505 * NOTE: They aren't atomic. 506 */ 507 static inline uint8_t 508 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 509 { 510 uint8_t val = pci_get_byte(config); 511 pci_set_byte(config, val & ~mask); 512 return val & mask; 513 } 514 515 static inline uint8_t 516 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 517 { 518 uint8_t val = pci_get_byte(config); 519 pci_set_byte(config, val | mask); 520 return val & mask; 521 } 522 523 static inline uint16_t 524 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 525 { 526 uint16_t val = pci_get_word(config); 527 pci_set_word(config, val & ~mask); 528 return val & mask; 529 } 530 531 static inline uint16_t 532 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 533 { 534 uint16_t val = pci_get_word(config); 535 pci_set_word(config, val | mask); 536 return val & mask; 537 } 538 539 static inline uint32_t 540 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 541 { 542 uint32_t val = pci_get_long(config); 543 pci_set_long(config, val & ~mask); 544 return val & mask; 545 } 546 547 static inline uint32_t 548 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 549 { 550 uint32_t val = pci_get_long(config); 551 pci_set_long(config, val | mask); 552 return val & mask; 553 } 554 555 static inline uint64_t 556 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 557 { 558 uint64_t val = pci_get_quad(config); 559 pci_set_quad(config, val & ~mask); 560 return val & mask; 561 } 562 563 static inline uint64_t 564 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 565 { 566 uint64_t val = pci_get_quad(config); 567 pci_set_quad(config, val | mask); 568 return val & mask; 569 } 570 571 /* Access a register specified by a mask */ 572 static inline void 573 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 574 { 575 uint8_t val = pci_get_byte(config); 576 uint8_t rval = reg << (ffs(mask) - 1); 577 pci_set_byte(config, (~mask & val) | (mask & rval)); 578 } 579 580 static inline uint8_t 581 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 582 { 583 uint8_t val = pci_get_byte(config); 584 return (val & mask) >> (ffs(mask) - 1); 585 } 586 587 static inline void 588 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 589 { 590 uint16_t val = pci_get_word(config); 591 uint16_t rval = reg << (ffs(mask) - 1); 592 pci_set_word(config, (~mask & val) | (mask & rval)); 593 } 594 595 static inline uint16_t 596 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 597 { 598 uint16_t val = pci_get_word(config); 599 return (val & mask) >> (ffs(mask) - 1); 600 } 601 602 static inline void 603 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 604 { 605 uint32_t val = pci_get_long(config); 606 uint32_t rval = reg << (ffs(mask) - 1); 607 pci_set_long(config, (~mask & val) | (mask & rval)); 608 } 609 610 static inline uint32_t 611 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 612 { 613 uint32_t val = pci_get_long(config); 614 return (val & mask) >> (ffs(mask) - 1); 615 } 616 617 static inline void 618 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 619 { 620 uint64_t val = pci_get_quad(config); 621 uint64_t rval = reg << (ffs(mask) - 1); 622 pci_set_quad(config, (~mask & val) | (mask & rval)); 623 } 624 625 static inline uint64_t 626 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 627 { 628 uint64_t val = pci_get_quad(config); 629 return (val & mask) >> (ffs(mask) - 1); 630 } 631 632 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 633 const char *name); 634 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 635 bool multifunction, 636 const char *name); 637 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 638 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 639 640 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 641 void pci_set_irq(PCIDevice *pci_dev, int level); 642 643 static inline void pci_irq_assert(PCIDevice *pci_dev) 644 { 645 pci_set_irq(pci_dev, 1); 646 } 647 648 static inline void pci_irq_deassert(PCIDevice *pci_dev) 649 { 650 pci_set_irq(pci_dev, 0); 651 } 652 653 /* 654 * FIXME: PCI does not work this way. 655 * All the callers to this method should be fixed. 656 */ 657 static inline void pci_irq_pulse(PCIDevice *pci_dev) 658 { 659 pci_irq_assert(pci_dev); 660 pci_irq_deassert(pci_dev); 661 } 662 663 static inline int pci_is_express(const PCIDevice *d) 664 { 665 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 666 } 667 668 static inline uint32_t pci_config_size(const PCIDevice *d) 669 { 670 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 671 } 672 673 /* DMA access functions */ 674 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 675 { 676 return &dev->bus_master_as; 677 } 678 679 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 680 void *buf, dma_addr_t len, DMADirection dir) 681 { 682 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 683 return 0; 684 } 685 686 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 687 void *buf, dma_addr_t len) 688 { 689 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 690 } 691 692 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 693 const void *buf, dma_addr_t len) 694 { 695 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 696 } 697 698 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 699 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 700 dma_addr_t addr) \ 701 { \ 702 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 703 } \ 704 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 705 dma_addr_t addr, uint##_bits##_t val) \ 706 { \ 707 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 708 } 709 710 PCI_DMA_DEFINE_LDST(ub, b, 8); 711 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 712 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 713 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 714 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 715 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 716 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 717 718 #undef PCI_DMA_DEFINE_LDST 719 720 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 721 dma_addr_t *plen, DMADirection dir) 722 { 723 void *buf; 724 725 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 726 return buf; 727 } 728 729 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 730 DMADirection dir, dma_addr_t access_len) 731 { 732 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 733 } 734 735 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 736 int alloc_hint) 737 { 738 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 739 } 740 741 extern const VMStateDescription vmstate_pci_device; 742 743 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 744 .name = (stringify(_field)), \ 745 .size = sizeof(PCIDevice), \ 746 .vmsd = &vmstate_pci_device, \ 747 .flags = VMS_STRUCT, \ 748 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 749 } 750 751 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 752 .name = (stringify(_field)), \ 753 .size = sizeof(PCIDevice), \ 754 .vmsd = &vmstate_pci_device, \ 755 .flags = VMS_STRUCT|VMS_POINTER, \ 756 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 757 } 758 759 #endif 760