1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "hw/qdev.h" 5 #include "exec/memory.h" 6 #include "sysemu/dma.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 #include "hw/pci/pcie.h" 12 13 /* PCI bus */ 14 15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 16 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 18 #define PCI_FUNC(devfn) ((devfn) & 0x07) 19 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 20 #define PCI_BUS_MAX 256 21 #define PCI_DEVFN_MAX 256 22 #define PCI_SLOT_MAX 32 23 #define PCI_FUNC_MAX 8 24 25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 26 #include "hw/pci/pci_ids.h" 27 28 /* QEMU-specific Vendor and Device ID definitions */ 29 30 /* IBM (0x1014) */ 31 #define PCI_DEVICE_ID_IBM_440GX 0x027f 32 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 33 34 /* Hitachi (0x1054) */ 35 #define PCI_VENDOR_ID_HITACHI 0x1054 36 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 37 38 /* Apple (0x106b) */ 39 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 43 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 44 45 /* Realtek (0x10ec) */ 46 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 47 48 /* Xilinx (0x10ee) */ 49 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 50 51 /* Marvell (0x11ab) */ 52 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 53 54 /* QEMU/Bochs VGA (0x1234) */ 55 #define PCI_VENDOR_ID_QEMU 0x1234 56 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 57 58 /* VMWare (0x15ad) */ 59 #define PCI_VENDOR_ID_VMWARE 0x15ad 60 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 61 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 62 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 63 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 64 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 65 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 66 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 67 68 /* Intel (0x8086) */ 69 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 70 #define PCI_DEVICE_ID_INTEL_82557 0x1229 71 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 72 73 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 74 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBDEVICE_ID_QEMU 0x1100 77 78 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 79 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 80 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 81 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 82 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 83 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 84 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 85 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 86 87 #define PCI_VENDOR_ID_REDHAT 0x1b36 88 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 89 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 90 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 91 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 92 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 93 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 94 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 95 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 96 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 97 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 98 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 99 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 100 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 101 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 102 103 #define FMT_PCIBUS PRIx64 104 105 typedef uint64_t pcibus_t; 106 107 struct PCIHostDeviceAddress { 108 unsigned int domain; 109 unsigned int bus; 110 unsigned int slot; 111 unsigned int function; 112 }; 113 114 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 115 uint32_t address, uint32_t data, int len); 116 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 117 uint32_t address, int len); 118 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 119 pcibus_t addr, pcibus_t size, int type); 120 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 121 122 typedef struct PCIIORegion { 123 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 124 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 125 pcibus_t size; 126 uint8_t type; 127 MemoryRegion *memory; 128 MemoryRegion *address_space; 129 } PCIIORegion; 130 131 #define PCI_ROM_SLOT 6 132 #define PCI_NUM_REGIONS 7 133 134 enum { 135 QEMU_PCI_VGA_MEM, 136 QEMU_PCI_VGA_IO_LO, 137 QEMU_PCI_VGA_IO_HI, 138 QEMU_PCI_VGA_NUM_REGIONS, 139 }; 140 141 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 142 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 143 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 144 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 145 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 146 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 147 148 #include "hw/pci/pci_regs.h" 149 150 /* PCI HEADER_TYPE */ 151 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 152 153 /* Size of the standard PCI config header */ 154 #define PCI_CONFIG_HEADER_SIZE 0x40 155 /* Size of the standard PCI config space */ 156 #define PCI_CONFIG_SPACE_SIZE 0x100 157 /* Size of the standard PCIe config space: 4KB */ 158 #define PCIE_CONFIG_SPACE_SIZE 0x1000 159 160 #define PCI_NUM_PINS 4 /* A-D */ 161 162 /* Bits in cap_present field. */ 163 enum { 164 QEMU_PCI_CAP_MSI = 0x1, 165 QEMU_PCI_CAP_MSIX = 0x2, 166 QEMU_PCI_CAP_EXPRESS = 0x4, 167 168 /* multifunction capable device */ 169 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 170 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 171 172 /* command register SERR bit enabled */ 173 #define QEMU_PCI_CAP_SERR_BITNR 4 174 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 175 /* Standard hot plug controller. */ 176 #define QEMU_PCI_SHPC_BITNR 5 177 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 178 #define QEMU_PCI_SLOTID_BITNR 6 179 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 180 /* PCI Express capability - Power Controller Present */ 181 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 182 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 183 /* Link active status in endpoint capability is always set */ 184 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 185 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 186 }; 187 188 #define TYPE_PCI_DEVICE "pci-device" 189 #define PCI_DEVICE(obj) \ 190 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 191 #define PCI_DEVICE_CLASS(klass) \ 192 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 193 #define PCI_DEVICE_GET_CLASS(obj) \ 194 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 195 196 typedef struct PCIINTxRoute { 197 enum { 198 PCI_INTX_ENABLED, 199 PCI_INTX_INVERTED, 200 PCI_INTX_DISABLED, 201 } mode; 202 int irq; 203 } PCIINTxRoute; 204 205 typedef struct PCIDeviceClass { 206 DeviceClass parent_class; 207 208 void (*realize)(PCIDevice *dev, Error **errp); 209 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 210 PCIUnregisterFunc *exit; 211 PCIConfigReadFunc *config_read; 212 PCIConfigWriteFunc *config_write; 213 214 uint16_t vendor_id; 215 uint16_t device_id; 216 uint8_t revision; 217 uint16_t class_id; 218 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 219 uint16_t subsystem_id; /* only for header type = 0 */ 220 221 /* 222 * pci-to-pci bridge or normal device. 223 * This doesn't mean pci host switch. 224 * When card bus bridge is supported, this would be enhanced. 225 */ 226 int is_bridge; 227 228 /* pcie stuff */ 229 int is_express; /* is this device pci express? */ 230 231 /* rom bar */ 232 const char *romfile; 233 } PCIDeviceClass; 234 235 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 236 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 237 MSIMessage msg); 238 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 239 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 240 unsigned int vector_start, 241 unsigned int vector_end); 242 243 enum PCIReqIDType { 244 PCI_REQ_ID_INVALID = 0, 245 PCI_REQ_ID_BDF, 246 PCI_REQ_ID_SECONDARY_BUS, 247 PCI_REQ_ID_MAX, 248 }; 249 typedef enum PCIReqIDType PCIReqIDType; 250 251 struct PCIReqIDCache { 252 PCIDevice *dev; 253 PCIReqIDType type; 254 }; 255 typedef struct PCIReqIDCache PCIReqIDCache; 256 257 struct PCIDevice { 258 DeviceState qdev; 259 260 /* PCI config space */ 261 uint8_t *config; 262 263 /* Used to enable config checks on load. Note that writable bits are 264 * never checked even if set in cmask. */ 265 uint8_t *cmask; 266 267 /* Used to implement R/W bytes */ 268 uint8_t *wmask; 269 270 /* Used to implement RW1C(Write 1 to Clear) bytes */ 271 uint8_t *w1cmask; 272 273 /* Used to allocate config space for capabilities. */ 274 uint8_t *used; 275 276 /* the following fields are read only */ 277 PCIBus *bus; 278 int32_t devfn; 279 /* Cached device to fetch requester ID from, to avoid the PCI 280 * tree walking every time we invoke PCI request (e.g., 281 * MSI). For conventional PCI root complex, this field is 282 * meaningless. */ 283 PCIReqIDCache requester_id_cache; 284 char name[64]; 285 PCIIORegion io_regions[PCI_NUM_REGIONS]; 286 AddressSpace bus_master_as; 287 MemoryRegion bus_master_enable_region; 288 289 /* do not access the following fields */ 290 PCIConfigReadFunc *config_read; 291 PCIConfigWriteFunc *config_write; 292 293 /* Legacy PCI VGA regions */ 294 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 295 bool has_vga; 296 297 /* Current IRQ levels. Used internally by the generic PCI code. */ 298 uint8_t irq_state; 299 300 /* Capability bits */ 301 uint32_t cap_present; 302 303 /* Offset of MSI-X capability in config space */ 304 uint8_t msix_cap; 305 306 /* MSI-X entries */ 307 int msix_entries_nr; 308 309 /* Space to store MSIX table & pending bit array */ 310 uint8_t *msix_table; 311 uint8_t *msix_pba; 312 /* MemoryRegion container for msix exclusive BAR setup */ 313 MemoryRegion msix_exclusive_bar; 314 /* Memory Regions for MSIX table and pending bit entries. */ 315 MemoryRegion msix_table_mmio; 316 MemoryRegion msix_pba_mmio; 317 /* Reference-count for entries actually in use by driver. */ 318 unsigned *msix_entry_used; 319 /* MSIX function mask set or MSIX disabled */ 320 bool msix_function_masked; 321 /* Version id needed for VMState */ 322 int32_t version_id; 323 324 /* Offset of MSI capability in config space */ 325 uint8_t msi_cap; 326 327 /* PCI Express */ 328 PCIExpressDevice exp; 329 330 /* SHPC */ 331 SHPCDevice *shpc; 332 333 /* Location of option rom */ 334 char *romfile; 335 bool has_rom; 336 MemoryRegion rom; 337 uint32_t rom_bar; 338 339 /* INTx routing notifier */ 340 PCIINTxRoutingNotifier intx_routing_notifier; 341 342 /* MSI-X notifiers */ 343 MSIVectorUseNotifier msix_vector_use_notifier; 344 MSIVectorReleaseNotifier msix_vector_release_notifier; 345 MSIVectorPollNotifier msix_vector_poll_notifier; 346 }; 347 348 void pci_register_bar(PCIDevice *pci_dev, int region_num, 349 uint8_t attr, MemoryRegion *memory); 350 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 351 MemoryRegion *io_lo, MemoryRegion *io_hi); 352 void pci_unregister_vga(PCIDevice *pci_dev); 353 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 354 355 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 356 uint8_t offset, uint8_t size); 357 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 358 uint8_t offset, uint8_t size, 359 Error **errp); 360 361 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 362 363 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 364 365 366 uint32_t pci_default_read_config(PCIDevice *d, 367 uint32_t address, int len); 368 void pci_default_write_config(PCIDevice *d, 369 uint32_t address, uint32_t val, int len); 370 void pci_device_save(PCIDevice *s, QEMUFile *f); 371 int pci_device_load(PCIDevice *s, QEMUFile *f); 372 MemoryRegion *pci_address_space(PCIDevice *dev); 373 MemoryRegion *pci_address_space_io(PCIDevice *dev); 374 375 /* 376 * Should not normally be used by devices. For use by sPAPR target 377 * where QEMU emulates firmware. 378 */ 379 int pci_bar(PCIDevice *d, int reg); 380 381 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 382 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 383 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 384 385 #define TYPE_PCI_BUS "PCI" 386 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 387 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 388 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 389 #define TYPE_PCIE_BUS "PCIE" 390 391 bool pci_bus_is_express(PCIBus *bus); 392 bool pci_bus_is_root(PCIBus *bus); 393 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 394 const char *name, 395 MemoryRegion *address_space_mem, 396 MemoryRegion *address_space_io, 397 uint8_t devfn_min, const char *typename); 398 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 399 MemoryRegion *address_space_mem, 400 MemoryRegion *address_space_io, 401 uint8_t devfn_min, const char *typename); 402 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 403 void *irq_opaque, int nirq); 404 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 405 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 406 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 407 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 408 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 409 void *irq_opaque, 410 MemoryRegion *address_space_mem, 411 MemoryRegion *address_space_io, 412 uint8_t devfn_min, int nirq, const char *typename); 413 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 414 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 415 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 416 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 417 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 418 PCIINTxRoutingNotifier notifier); 419 void pci_device_reset(PCIDevice *dev); 420 421 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 422 const char *default_model, 423 const char *default_devaddr); 424 425 PCIDevice *pci_vga_init(PCIBus *bus); 426 427 int pci_bus_num(PCIBus *s); 428 int pci_bus_numa_node(PCIBus *bus); 429 void pci_for_each_device(PCIBus *bus, int bus_num, 430 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 431 void *opaque); 432 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 433 void (*fn)(PCIBus *bus, PCIDevice *d, 434 void *opaque), 435 void *opaque); 436 void pci_for_each_bus_depth_first(PCIBus *bus, 437 void *(*begin)(PCIBus *bus, void *parent_state), 438 void (*end)(PCIBus *bus, void *state), 439 void *parent_state); 440 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 441 442 /* Use this wrapper when specific scan order is not required. */ 443 static inline 444 void pci_for_each_bus(PCIBus *bus, 445 void (*fn)(PCIBus *bus, void *opaque), 446 void *opaque) 447 { 448 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 449 } 450 451 PCIBus *pci_find_primary_bus(void); 452 PCIBus *pci_device_root_bus(const PCIDevice *d); 453 const char *pci_root_bus_path(PCIDevice *dev); 454 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 455 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 456 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 457 458 void pci_device_deassert_intx(PCIDevice *dev); 459 460 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 461 462 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 463 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 464 465 static inline void 466 pci_set_byte(uint8_t *config, uint8_t val) 467 { 468 *config = val; 469 } 470 471 static inline uint8_t 472 pci_get_byte(const uint8_t *config) 473 { 474 return *config; 475 } 476 477 static inline void 478 pci_set_word(uint8_t *config, uint16_t val) 479 { 480 stw_le_p(config, val); 481 } 482 483 static inline uint16_t 484 pci_get_word(const uint8_t *config) 485 { 486 return lduw_le_p(config); 487 } 488 489 static inline void 490 pci_set_long(uint8_t *config, uint32_t val) 491 { 492 stl_le_p(config, val); 493 } 494 495 static inline uint32_t 496 pci_get_long(const uint8_t *config) 497 { 498 return ldl_le_p(config); 499 } 500 501 /* 502 * PCI capabilities and/or their fields 503 * are generally DWORD aligned only so 504 * mechanism used by pci_set/get_quad() 505 * must be tolerant to unaligned pointers 506 * 507 */ 508 static inline void 509 pci_set_quad(uint8_t *config, uint64_t val) 510 { 511 stq_le_p(config, val); 512 } 513 514 static inline uint64_t 515 pci_get_quad(const uint8_t *config) 516 { 517 return ldq_le_p(config); 518 } 519 520 static inline void 521 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 522 { 523 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 524 } 525 526 static inline void 527 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 528 { 529 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 530 } 531 532 static inline void 533 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 534 { 535 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 536 } 537 538 static inline void 539 pci_config_set_class(uint8_t *pci_config, uint16_t val) 540 { 541 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 542 } 543 544 static inline void 545 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 546 { 547 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 548 } 549 550 static inline void 551 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 552 { 553 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 554 } 555 556 /* 557 * helper functions to do bit mask operation on configuration space. 558 * Just to set bit, use test-and-set and discard returned value. 559 * Just to clear bit, use test-and-clear and discard returned value. 560 * NOTE: They aren't atomic. 561 */ 562 static inline uint8_t 563 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 564 { 565 uint8_t val = pci_get_byte(config); 566 pci_set_byte(config, val & ~mask); 567 return val & mask; 568 } 569 570 static inline uint8_t 571 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 572 { 573 uint8_t val = pci_get_byte(config); 574 pci_set_byte(config, val | mask); 575 return val & mask; 576 } 577 578 static inline uint16_t 579 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 580 { 581 uint16_t val = pci_get_word(config); 582 pci_set_word(config, val & ~mask); 583 return val & mask; 584 } 585 586 static inline uint16_t 587 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 588 { 589 uint16_t val = pci_get_word(config); 590 pci_set_word(config, val | mask); 591 return val & mask; 592 } 593 594 static inline uint32_t 595 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 596 { 597 uint32_t val = pci_get_long(config); 598 pci_set_long(config, val & ~mask); 599 return val & mask; 600 } 601 602 static inline uint32_t 603 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 604 { 605 uint32_t val = pci_get_long(config); 606 pci_set_long(config, val | mask); 607 return val & mask; 608 } 609 610 static inline uint64_t 611 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 612 { 613 uint64_t val = pci_get_quad(config); 614 pci_set_quad(config, val & ~mask); 615 return val & mask; 616 } 617 618 static inline uint64_t 619 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 620 { 621 uint64_t val = pci_get_quad(config); 622 pci_set_quad(config, val | mask); 623 return val & mask; 624 } 625 626 /* Access a register specified by a mask */ 627 static inline void 628 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 629 { 630 uint8_t val = pci_get_byte(config); 631 uint8_t rval = reg << ctz32(mask); 632 pci_set_byte(config, (~mask & val) | (mask & rval)); 633 } 634 635 static inline uint8_t 636 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 637 { 638 uint8_t val = pci_get_byte(config); 639 return (val & mask) >> ctz32(mask); 640 } 641 642 static inline void 643 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 644 { 645 uint16_t val = pci_get_word(config); 646 uint16_t rval = reg << ctz32(mask); 647 pci_set_word(config, (~mask & val) | (mask & rval)); 648 } 649 650 static inline uint16_t 651 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 652 { 653 uint16_t val = pci_get_word(config); 654 return (val & mask) >> ctz32(mask); 655 } 656 657 static inline void 658 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 659 { 660 uint32_t val = pci_get_long(config); 661 uint32_t rval = reg << ctz32(mask); 662 pci_set_long(config, (~mask & val) | (mask & rval)); 663 } 664 665 static inline uint32_t 666 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 667 { 668 uint32_t val = pci_get_long(config); 669 return (val & mask) >> ctz32(mask); 670 } 671 672 static inline void 673 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 674 { 675 uint64_t val = pci_get_quad(config); 676 uint64_t rval = reg << ctz32(mask); 677 pci_set_quad(config, (~mask & val) | (mask & rval)); 678 } 679 680 static inline uint64_t 681 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 682 { 683 uint64_t val = pci_get_quad(config); 684 return (val & mask) >> ctz32(mask); 685 } 686 687 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 688 const char *name); 689 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 690 bool multifunction, 691 const char *name); 692 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 693 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 694 695 void lsi53c895a_create(PCIBus *bus); 696 697 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 698 void pci_set_irq(PCIDevice *pci_dev, int level); 699 700 static inline void pci_irq_assert(PCIDevice *pci_dev) 701 { 702 pci_set_irq(pci_dev, 1); 703 } 704 705 static inline void pci_irq_deassert(PCIDevice *pci_dev) 706 { 707 pci_set_irq(pci_dev, 0); 708 } 709 710 /* 711 * FIXME: PCI does not work this way. 712 * All the callers to this method should be fixed. 713 */ 714 static inline void pci_irq_pulse(PCIDevice *pci_dev) 715 { 716 pci_irq_assert(pci_dev); 717 pci_irq_deassert(pci_dev); 718 } 719 720 static inline int pci_is_express(const PCIDevice *d) 721 { 722 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 723 } 724 725 static inline uint32_t pci_config_size(const PCIDevice *d) 726 { 727 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 728 } 729 730 static inline uint16_t pci_get_bdf(PCIDevice *dev) 731 { 732 return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); 733 } 734 735 uint16_t pci_requester_id(PCIDevice *dev); 736 737 /* DMA access functions */ 738 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 739 { 740 return &dev->bus_master_as; 741 } 742 743 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 744 void *buf, dma_addr_t len, DMADirection dir) 745 { 746 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 747 return 0; 748 } 749 750 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 751 void *buf, dma_addr_t len) 752 { 753 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 754 } 755 756 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 757 const void *buf, dma_addr_t len) 758 { 759 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 760 } 761 762 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 763 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 764 dma_addr_t addr) \ 765 { \ 766 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 767 } \ 768 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 769 dma_addr_t addr, uint##_bits##_t val) \ 770 { \ 771 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 772 } 773 774 PCI_DMA_DEFINE_LDST(ub, b, 8); 775 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 776 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 777 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 778 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 779 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 780 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 781 782 #undef PCI_DMA_DEFINE_LDST 783 784 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 785 dma_addr_t *plen, DMADirection dir) 786 { 787 void *buf; 788 789 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 790 return buf; 791 } 792 793 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 794 DMADirection dir, dma_addr_t access_len) 795 { 796 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 797 } 798 799 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 800 int alloc_hint) 801 { 802 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 803 } 804 805 extern const VMStateDescription vmstate_pci_device; 806 807 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 808 .name = (stringify(_field)), \ 809 .size = sizeof(PCIDevice), \ 810 .vmsd = &vmstate_pci_device, \ 811 .flags = VMS_STRUCT, \ 812 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 813 } 814 815 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 816 .name = (stringify(_field)), \ 817 .size = sizeof(PCIDevice), \ 818 .vmsd = &vmstate_pci_device, \ 819 .flags = VMS_STRUCT|VMS_POINTER, \ 820 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 821 } 822 823 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 824 825 #endif 826