1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "system/memory.h" 5 #include "system/dma.h" 6 #include "system/host_iommu_device.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 extern bool pci_available; 12 13 /* PCI bus */ 14 15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 16 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 18 #define PCI_FUNC(devfn) ((devfn) & 0x07) 19 #define PCI_BUILD_BDF(bus, devfn) (((bus) << 8) | (devfn)) 20 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 21 #define PCI_BUS_MAX 256 22 #define PCI_DEVFN_MAX 256 23 #define PCI_SLOT_MAX 32 24 #define PCI_FUNC_MAX 8 25 26 #define PCI_SBDF(seg, bus, dev, func) \ 27 ((((uint32_t)(seg)) << 16) | \ 28 (PCI_BUILD_BDF(bus, PCI_DEVFN(dev, func)))) 29 30 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 31 #include "hw/pci/pci_ids.h" 32 33 /* QEMU-specific Vendor and Device ID definitions */ 34 35 /* IBM (0x1014) */ 36 #define PCI_DEVICE_ID_IBM_440GX 0x027f 37 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 38 39 /* Hitachi (0x1054) */ 40 #define PCI_VENDOR_ID_HITACHI 0x1054 41 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 42 43 /* Apple (0x106b) */ 44 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 45 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 46 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 47 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 48 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 49 50 /* Realtek (0x10ec) */ 51 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 52 53 /* Xilinx (0x10ee) */ 54 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 55 56 /* Marvell (0x11ab) */ 57 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 58 59 /* QEMU/Bochs VGA (0x1234) */ 60 #define PCI_VENDOR_ID_QEMU 0x1234 61 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 62 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 63 64 /* VMWare (0x15ad) */ 65 #define PCI_VENDOR_ID_VMWARE 0x15ad 66 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 67 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 68 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 69 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 70 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 71 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 72 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 73 74 /* Intel (0x8086) */ 75 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 76 #define PCI_DEVICE_ID_INTEL_82557 0x1229 77 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 78 79 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 80 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 81 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 82 #define PCI_SUBDEVICE_ID_QEMU 0x1100 83 84 /* legacy virtio-pci devices */ 85 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 86 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 87 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 88 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 89 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 90 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 91 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 92 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 93 94 /* 95 * modern virtio-pci devices get their id assigned automatically, 96 * there is no need to add #defines here. It gets calculated as 97 * 98 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + 99 * virtio_bus_get_vdev_id(bus) 100 */ 101 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 102 103 #define PCI_VENDOR_ID_REDHAT 0x1b36 104 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 105 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 106 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 107 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 108 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 109 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 110 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 111 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 112 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 113 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 114 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 115 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 116 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 117 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 118 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 119 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 120 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 121 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 122 #define PCI_DEVICE_ID_REDHAT_UFS 0x0013 123 #define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014 124 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 125 126 #define FMT_PCIBUS PRIx64 127 128 typedef uint64_t pcibus_t; 129 130 struct PCIHostDeviceAddress { 131 unsigned int domain; 132 unsigned int bus; 133 unsigned int slot; 134 unsigned int function; 135 }; 136 137 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 138 uint32_t address, uint32_t data, int len); 139 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 140 uint32_t address, int len); 141 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 142 pcibus_t addr, pcibus_t size, int type); 143 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 144 145 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 146 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 147 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 148 149 typedef struct PCIIORegion { 150 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 151 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 152 pcibus_t size; 153 uint8_t type; 154 MemoryRegion *memory; 155 MemoryRegion *address_space; 156 } PCIIORegion; 157 158 #define PCI_ROM_SLOT 6 159 #define PCI_NUM_REGIONS 7 160 161 enum { 162 QEMU_PCI_VGA_MEM, 163 QEMU_PCI_VGA_IO_LO, 164 QEMU_PCI_VGA_IO_HI, 165 QEMU_PCI_VGA_NUM_REGIONS, 166 }; 167 168 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 169 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 170 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 171 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 172 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 173 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 174 175 #include "hw/pci/pci_regs.h" 176 177 /* PCI HEADER_TYPE */ 178 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 179 180 /* Size of the standard PCI config header */ 181 #define PCI_CONFIG_HEADER_SIZE 0x40 182 /* Size of the standard PCI config space */ 183 #define PCI_CONFIG_SPACE_SIZE 0x100 184 /* Size of the standard PCIe config space: 4KB */ 185 #define PCIE_CONFIG_SPACE_SIZE 0x1000 186 187 #define PCI_NUM_PINS 4 /* A-D */ 188 189 /* Bits in cap_present field. */ 190 enum { 191 QEMU_PCI_CAP_MSI = 0x1, 192 QEMU_PCI_CAP_MSIX = 0x2, 193 QEMU_PCI_CAP_EXPRESS = 0x4, 194 195 /* multifunction capable device */ 196 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 197 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 198 199 /* command register SERR bit enabled - unused since QEMU v5.0 */ 200 #define QEMU_PCI_CAP_SERR_BITNR 4 201 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 202 /* Standard hot plug controller. */ 203 #define QEMU_PCI_SHPC_BITNR 5 204 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 205 #define QEMU_PCI_SLOTID_BITNR 6 206 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 207 /* PCI Express capability - Power Controller Present */ 208 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 209 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 210 /* Link active status in endpoint capability is always set */ 211 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 212 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 213 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 214 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 215 #define QEMU_PCIE_CXL_BITNR 10 216 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 217 #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 218 QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), 219 #define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 220 QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), 221 #define QEMU_PCIE_EXT_TAG_BITNR 13 222 QEMU_PCIE_EXT_TAG = (1 << QEMU_PCIE_EXT_TAG_BITNR), 223 #define QEMU_PCI_CAP_PM_BITNR 14 224 QEMU_PCI_CAP_PM = (1 << QEMU_PCI_CAP_PM_BITNR), 225 #define QEMU_PCI_SKIP_RESET_ON_CPR_BITNR 15 226 QEMU_PCI_SKIP_RESET_ON_CPR = (1 << QEMU_PCI_SKIP_RESET_ON_CPR_BITNR), 227 }; 228 229 typedef struct PCIINTxRoute { 230 enum { 231 PCI_INTX_ENABLED, 232 PCI_INTX_INVERTED, 233 PCI_INTX_DISABLED, 234 } mode; 235 int irq; 236 } PCIINTxRoute; 237 238 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 239 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 240 MSIMessage msg); 241 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 242 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 243 unsigned int vector_start, 244 unsigned int vector_end); 245 246 void pci_register_bar(PCIDevice *pci_dev, int region_num, 247 uint8_t attr, MemoryRegion *memory); 248 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 249 MemoryRegion *io_lo, MemoryRegion *io_hi); 250 void pci_unregister_vga(PCIDevice *pci_dev); 251 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 252 253 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 254 uint8_t offset, uint8_t size, 255 Error **errp); 256 257 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 258 259 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 260 261 262 uint32_t pci_default_read_config(PCIDevice *d, 263 uint32_t address, int len); 264 void pci_default_write_config(PCIDevice *d, 265 uint32_t address, uint32_t val, int len); 266 void pci_device_save(PCIDevice *s, QEMUFile *f); 267 int pci_device_load(PCIDevice *s, QEMUFile *f); 268 MemoryRegion *pci_address_space(PCIDevice *dev); 269 MemoryRegion *pci_address_space_io(PCIDevice *dev); 270 271 /* 272 * Should not normally be used by devices. For use by sPAPR target 273 * where QEMU emulates firmware. 274 */ 275 int pci_bar(PCIDevice *d, int reg); 276 277 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 278 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 279 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 280 281 #define TYPE_PCI_BUS "PCI" 282 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 283 #define TYPE_PCIE_BUS "PCIE" 284 #define TYPE_CXL_BUS "CXL" 285 286 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 287 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 288 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 289 290 bool pci_bus_is_express(const PCIBus *bus); 291 292 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 293 const char *name, 294 MemoryRegion *mem, MemoryRegion *io, 295 uint8_t devfn_min, const char *typename); 296 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 297 MemoryRegion *mem, MemoryRegion *io, 298 uint8_t devfn_min, const char *typename); 299 void pci_root_bus_cleanup(PCIBus *bus); 300 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 301 void *irq_opaque, int nirq); 302 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq); 303 void pci_bus_irqs_cleanup(PCIBus *bus); 304 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 305 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus); 306 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask); 307 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask); 308 bool pci_bus_add_fw_cfg_extra_pci_roots(FWCfgState *fw_cfg, 309 PCIBus *bus, 310 Error **errp); 311 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 312 static inline int pci_swizzle(int slot, int pin) 313 { 314 return (slot + pin) % PCI_NUM_PINS; 315 } 316 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 317 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 318 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 319 void *irq_opaque, 320 MemoryRegion *mem, MemoryRegion *io, 321 uint8_t devfn_min, int nirq, 322 const char *typename); 323 void pci_unregister_root_bus(PCIBus *bus); 324 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 325 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 326 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 327 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 328 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 329 PCIINTxRoutingNotifier notifier); 330 void pci_device_reset(PCIDevice *dev); 331 332 void pci_init_nic_devices(PCIBus *bus, const char *default_model); 333 bool pci_init_nic_in_slot(PCIBus *rootbus, const char *default_model, 334 const char *alias, const char *devaddr); 335 PCIDevice *pci_vga_init(PCIBus *bus); 336 337 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 338 { 339 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 340 } 341 int pci_bus_num(PCIBus *s); 342 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 343 static inline int pci_dev_bus_num(const PCIDevice *dev) 344 { 345 return pci_bus_num(pci_get_bus(dev)); 346 } 347 348 int pci_bus_numa_node(PCIBus *bus); 349 void pci_for_each_device(PCIBus *bus, int bus_num, 350 pci_bus_dev_fn fn, 351 void *opaque); 352 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 353 pci_bus_dev_fn fn, 354 void *opaque); 355 void pci_for_each_device_under_bus(PCIBus *bus, 356 pci_bus_dev_fn fn, void *opaque); 357 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 358 pci_bus_dev_fn fn, 359 void *opaque); 360 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 361 pci_bus_fn end, void *parent_state); 362 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 363 364 /* Use this wrapper when specific scan order is not required. */ 365 static inline 366 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 367 { 368 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 369 } 370 371 PCIBus *pci_device_root_bus(const PCIDevice *d); 372 const char *pci_root_bus_path(PCIDevice *dev); 373 bool pci_bus_bypass_iommu(PCIBus *bus); 374 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 375 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 376 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 377 378 void pci_device_deassert_intx(PCIDevice *dev); 379 380 /* Page Request Interface */ 381 typedef enum { 382 IOMMU_PRI_RESP_SUCCESS, 383 IOMMU_PRI_RESP_INVALID_REQUEST, 384 IOMMU_PRI_RESP_FAILURE, 385 } IOMMUPRIResponseCode; 386 387 typedef struct IOMMUPRIResponse { 388 IOMMUPRIResponseCode response_code; 389 uint16_t prgi; 390 } IOMMUPRIResponse; 391 392 struct IOMMUPRINotifier; 393 394 typedef void (*IOMMUPRINotify)(struct IOMMUPRINotifier *notifier, 395 IOMMUPRIResponse *response); 396 397 typedef struct IOMMUPRINotifier { 398 IOMMUPRINotify notify; 399 } IOMMUPRINotifier; 400 401 #define PCI_PRI_PRGI_MASK 0x1ffU 402 403 /** 404 * struct PCIIOMMUOps: callbacks structure for specific IOMMU handlers 405 * of a PCIBus 406 * 407 * Allows to modify the behavior of some IOMMU operations of the PCI 408 * framework for a set of devices on a PCI bus. 409 */ 410 typedef struct PCIIOMMUOps { 411 /** 412 * @get_address_space: get the address space for a set of devices 413 * on a PCI bus. 414 * 415 * Mandatory callback which returns a pointer to an #AddressSpace 416 * 417 * @bus: the #PCIBus being accessed. 418 * 419 * @opaque: the data passed to pci_setup_iommu(). 420 * 421 * @devfn: device and function number 422 */ 423 AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn); 424 /** 425 * @set_iommu_device: attach a HostIOMMUDevice to a vIOMMU 426 * 427 * Optional callback, if not implemented in vIOMMU, then vIOMMU can't 428 * retrieve host information from the associated HostIOMMUDevice. 429 * 430 * @bus: the #PCIBus of the PCI device. 431 * 432 * @opaque: the data passed to pci_setup_iommu(). 433 * 434 * @devfn: device and function number of the PCI device. 435 * 436 * @dev: the #HostIOMMUDevice to attach. 437 * 438 * @errp: pass an Error out only when return false 439 * 440 * Returns: true if HostIOMMUDevice is attached or else false with errp set. 441 */ 442 bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn, 443 HostIOMMUDevice *dev, Error **errp); 444 /** 445 * @unset_iommu_device: detach a HostIOMMUDevice from a vIOMMU 446 * 447 * Optional callback. 448 * 449 * @bus: the #PCIBus of the PCI device. 450 * 451 * @opaque: the data passed to pci_setup_iommu(). 452 * 453 * @devfn: device and function number of the PCI device. 454 */ 455 void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); 456 /** 457 * @get_iotlb_info: get properties required to initialize a device IOTLB. 458 * 459 * Callback required if devices are allowed to cache translations. 460 * 461 * @opaque: the data passed to pci_setup_iommu(). 462 * 463 * @addr_width: the address width of the IOMMU (output parameter). 464 * 465 * @min_page_size: the page size of the IOMMU (output parameter). 466 */ 467 void (*get_iotlb_info)(void *opaque, uint8_t *addr_width, 468 uint32_t *min_page_size); 469 /** 470 * @init_iotlb_notifier: initialize an IOMMU notifier. 471 * 472 * Optional callback. 473 * 474 * @bus: the #PCIBus of the PCI device. 475 * 476 * @opaque: the data passed to pci_setup_iommu(). 477 * 478 * @devfn: device and function number of the PCI device. 479 * 480 * @n: the notifier to be initialized. 481 * 482 * @fn: the callback to be installed. 483 * 484 * @user_opaque: a user pointer that can be used to track a state. 485 */ 486 void (*init_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, 487 IOMMUNotifier *n, IOMMUNotify fn, 488 void *user_opaque); 489 /** 490 * @register_iotlb_notifier: setup an IOTLB invalidation notifier. 491 * 492 * Callback required if devices are allowed to cache translations. 493 * 494 * @bus: the #PCIBus of the PCI device. 495 * 496 * @opaque: the data passed to pci_setup_iommu(). 497 * 498 * @devfn: device and function number of the PCI device. 499 * 500 * @pasid: the pasid of the address space to watch. 501 * 502 * @n: the notifier to register. 503 */ 504 void (*register_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, 505 uint32_t pasid, IOMMUNotifier *n); 506 /** 507 * @unregister_iotlb_notifier: remove an IOTLB invalidation notifier. 508 * 509 * Callback required if devices are allowed to cache translations. 510 * 511 * @bus: the #PCIBus of the PCI device. 512 * 513 * @opaque: the data passed to pci_setup_iommu(). 514 * 515 * @devfn: device and function number of the PCI device. 516 * 517 * @pasid: the pasid of the address space to stop watching. 518 * 519 * @n: the notifier to unregister. 520 */ 521 void (*unregister_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, 522 uint32_t pasid, IOMMUNotifier *n); 523 /** 524 * @ats_request_translation: issue an ATS request. 525 * 526 * Callback required if devices are allowed to use the address 527 * translation service. 528 * 529 * @bus: the #PCIBus of the PCI device. 530 * 531 * @opaque: the data passed to pci_setup_iommu(). 532 * 533 * @devfn: device and function number of the PCI device. 534 * 535 * @pasid: the pasid of the address space to use for the request. 536 * 537 * @priv_req: privileged mode bit (PASID TLP). 538 * 539 * @exec_req: execute request bit (PASID TLP). 540 * 541 * @addr: start address of the memory range to be translated. 542 * 543 * @length: length of the memory range in bytes. 544 * 545 * @no_write: request a read-only translation (if supported). 546 * 547 * @result: buffer in which the TLB entries will be stored. 548 * 549 * @result_length: result buffer length. 550 * 551 * @err_count: number of untranslated subregions. 552 * 553 * Returns: the number of translations stored in the result buffer, or 554 * -ENOMEM if the buffer is not large enough. 555 */ 556 ssize_t (*ats_request_translation)(PCIBus *bus, void *opaque, int devfn, 557 uint32_t pasid, bool priv_req, 558 bool exec_req, hwaddr addr, 559 size_t length, bool no_write, 560 IOMMUTLBEntry *result, 561 size_t result_length, 562 uint32_t *err_count); 563 /** 564 * @pri_register_notifier: setup the PRI completion callback. 565 * 566 * Callback required if devices are allowed to use the page request 567 * interface. 568 * 569 * @bus: the #PCIBus of the PCI device. 570 * 571 * @opaque: the data passed to pci_setup_iommu(). 572 * 573 * @devfn: device and function number of the PCI device. 574 * 575 * @pasid: the pasid of the address space to track. 576 * 577 * @notifier: the notifier to register. 578 */ 579 void (*pri_register_notifier)(PCIBus *bus, void *opaque, int devfn, 580 uint32_t pasid, IOMMUPRINotifier *notifier); 581 /** 582 * @pri_unregister_notifier: remove the PRI completion callback. 583 * 584 * Callback required if devices are allowed to use the page request 585 * interface. 586 * 587 * @bus: the #PCIBus of the PCI device. 588 * 589 * @opaque: the data passed to pci_setup_iommu(). 590 * 591 * @devfn: device and function number of the PCI device. 592 * 593 * @pasid: the pasid of the address space to stop tracking. 594 */ 595 void (*pri_unregister_notifier)(PCIBus *bus, void *opaque, int devfn, 596 uint32_t pasid); 597 /** 598 * @pri_request_page: issue a PRI request. 599 * 600 * Callback required if devices are allowed to use the page request 601 * interface. 602 * 603 * @bus: the #PCIBus of the PCI device. 604 * 605 * @opaque: the data passed to pci_setup_iommu(). 606 * 607 * @devfn: device and function number of the PCI device. 608 * 609 * @pasid: the pasid of the address space to use for the request. 610 * 611 * @priv_req: privileged mode bit (PASID TLP). 612 * 613 * @exec_req: execute request bit (PASID TLP). 614 * 615 * @addr: untranslated address of the requested page. 616 * 617 * @lpig: last page in group. 618 * 619 * @prgi: page request group index. 620 * 621 * @is_read: request read access. 622 * 623 * @is_write: request write access. 624 */ 625 int (*pri_request_page)(PCIBus *bus, void *opaque, int devfn, 626 uint32_t pasid, bool priv_req, bool exec_req, 627 hwaddr addr, bool lpig, uint16_t prgi, bool is_read, 628 bool is_write); 629 } PCIIOMMUOps; 630 631 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 632 bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, 633 Error **errp); 634 void pci_device_unset_iommu_device(PCIDevice *dev); 635 636 /** 637 * pci_iommu_get_iotlb_info: get properties required to initialize a 638 * device IOTLB. 639 * 640 * Returns 0 on success, or a negative errno otherwise. 641 * 642 * @dev: the device that wants to get the information. 643 * @addr_width: the address width of the IOMMU (output parameter). 644 * @min_page_size: the page size of the IOMMU (output parameter). 645 */ 646 int pci_iommu_get_iotlb_info(PCIDevice *dev, uint8_t *addr_width, 647 uint32_t *min_page_size); 648 649 /** 650 * pci_iommu_init_iotlb_notifier: initialize an IOMMU notifier. 651 * 652 * This function is used by devices before registering an IOTLB notifier. 653 * 654 * @dev: the device. 655 * @n: the notifier to be initialized. 656 * @fn: the callback to be installed. 657 * @opaque: a user pointer that can be used to track a state. 658 */ 659 int pci_iommu_init_iotlb_notifier(PCIDevice *dev, IOMMUNotifier *n, 660 IOMMUNotify fn, void *opaque); 661 662 /** 663 * pci_ats_request_translation: perform an ATS request. 664 * 665 * Returns the number of translations stored in @result in case of success, 666 * a negative error code otherwise. 667 * -ENOMEM is returned when the result buffer is not large enough to store 668 * all the translations. 669 * 670 * @dev: the ATS-capable PCI device. 671 * @pasid: the pasid of the address space in which the translation will be done. 672 * @priv_req: privileged mode bit (PASID TLP). 673 * @exec_req: execute request bit (PASID TLP). 674 * @addr: start address of the memory range to be translated. 675 * @length: length of the memory range in bytes. 676 * @no_write: request a read-only translation (if supported). 677 * @result: buffer in which the TLB entries will be stored. 678 * @result_length: result buffer length. 679 * @err_count: number of untranslated subregions. 680 */ 681 ssize_t pci_ats_request_translation(PCIDevice *dev, uint32_t pasid, 682 bool priv_req, bool exec_req, 683 hwaddr addr, size_t length, 684 bool no_write, IOMMUTLBEntry *result, 685 size_t result_length, 686 uint32_t *err_count); 687 688 /** 689 * pci_pri_request_page: perform a PRI request. 690 * 691 * Returns 0 if the PRI request has been sent to the guest OS, 692 * an error code otherwise. 693 * 694 * @dev: the PRI-capable PCI device. 695 * @pasid: the pasid of the address space in which the translation will be done. 696 * @priv_req: privileged mode bit (PASID TLP). 697 * @exec_req: execute request bit (PASID TLP). 698 * @addr: untranslated address of the requested page. 699 * @lpig: last page in group. 700 * @prgi: page request group index. 701 * @is_read: request read access. 702 * @is_write: request write access. 703 */ 704 int pci_pri_request_page(PCIDevice *dev, uint32_t pasid, bool priv_req, 705 bool exec_req, hwaddr addr, bool lpig, 706 uint16_t prgi, bool is_read, bool is_write); 707 708 /** 709 * pci_pri_register_notifier: register the PRI callback for a given address 710 * space. 711 * 712 * Returns 0 on success, an error code otherwise. 713 * 714 * @dev: the PRI-capable PCI device. 715 * @pasid: the pasid of the address space to track. 716 * @notifier: the notifier to register. 717 */ 718 int pci_pri_register_notifier(PCIDevice *dev, uint32_t pasid, 719 IOMMUPRINotifier *notifier); 720 721 /** 722 * pci_pri_unregister_notifier: remove the PRI callback from a given address 723 * space. 724 * 725 * @dev: the PRI-capable PCI device. 726 * @pasid: the pasid of the address space to stop tracking. 727 */ 728 void pci_pri_unregister_notifier(PCIDevice *dev, uint32_t pasid); 729 730 /** 731 * pci_iommu_register_iotlb_notifier: register a notifier for changes to 732 * IOMMU translation entries in a specific address space. 733 * 734 * Returns 0 on success, or a negative errno otherwise. 735 * 736 * @dev: the device that wants to get notified. 737 * @pasid: the pasid of the address space to track. 738 * @n: the notifier to register. 739 */ 740 int pci_iommu_register_iotlb_notifier(PCIDevice *dev, uint32_t pasid, 741 IOMMUNotifier *n); 742 743 /** 744 * pci_iommu_unregister_iotlb_notifier: unregister a notifier that has been 745 * registerd with pci_iommu_register_iotlb_notifier. 746 * 747 * Returns 0 on success, or a negative errno otherwise. 748 * 749 * @dev: the device that wants to stop notifications. 750 * @pasid: the pasid of the address space to stop tracking. 751 * @n: the notifier to unregister. 752 */ 753 int pci_iommu_unregister_iotlb_notifier(PCIDevice *dev, uint32_t pasid, 754 IOMMUNotifier *n); 755 756 /** 757 * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus 758 * 759 * Let PCI host bridges define specific operations. 760 * 761 * @bus: the #PCIBus being updated. 762 * @ops: the #PCIIOMMUOps 763 * @opaque: passed to callbacks of the @ops structure. 764 */ 765 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); 766 767 pcibus_t pci_bar_address(PCIDevice *d, 768 int reg, uint8_t type, pcibus_t size); 769 770 static inline void 771 pci_set_byte(uint8_t *config, uint8_t val) 772 { 773 *config = val; 774 } 775 776 static inline uint8_t 777 pci_get_byte(const uint8_t *config) 778 { 779 return *config; 780 } 781 782 static inline void 783 pci_set_word(uint8_t *config, uint16_t val) 784 { 785 stw_le_p(config, val); 786 } 787 788 static inline uint16_t 789 pci_get_word(const uint8_t *config) 790 { 791 return lduw_le_p(config); 792 } 793 794 static inline void 795 pci_set_long(uint8_t *config, uint32_t val) 796 { 797 stl_le_p(config, val); 798 } 799 800 static inline uint32_t 801 pci_get_long(const uint8_t *config) 802 { 803 return ldl_le_p(config); 804 } 805 806 /* 807 * PCI capabilities and/or their fields 808 * are generally DWORD aligned only so 809 * mechanism used by pci_set/get_quad() 810 * must be tolerant to unaligned pointers 811 * 812 */ 813 static inline void 814 pci_set_quad(uint8_t *config, uint64_t val) 815 { 816 stq_le_p(config, val); 817 } 818 819 static inline uint64_t 820 pci_get_quad(const uint8_t *config) 821 { 822 return ldq_le_p(config); 823 } 824 825 static inline void 826 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 827 { 828 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 829 } 830 831 static inline void 832 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 833 { 834 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 835 } 836 837 static inline void 838 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 839 { 840 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 841 } 842 843 static inline void 844 pci_config_set_class(uint8_t *pci_config, uint16_t val) 845 { 846 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 847 } 848 849 static inline void 850 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 851 { 852 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 853 } 854 855 static inline void 856 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 857 { 858 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 859 } 860 861 /* 862 * helper functions to do bit mask operation on configuration space. 863 * Just to set bit, use test-and-set and discard returned value. 864 * Just to clear bit, use test-and-clear and discard returned value. 865 * NOTE: They aren't atomic. 866 */ 867 static inline uint8_t 868 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 869 { 870 uint8_t val = pci_get_byte(config); 871 pci_set_byte(config, val & ~mask); 872 return val & mask; 873 } 874 875 static inline uint8_t 876 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 877 { 878 uint8_t val = pci_get_byte(config); 879 pci_set_byte(config, val | mask); 880 return val & mask; 881 } 882 883 static inline uint16_t 884 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 885 { 886 uint16_t val = pci_get_word(config); 887 pci_set_word(config, val & ~mask); 888 return val & mask; 889 } 890 891 static inline uint16_t 892 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 893 { 894 uint16_t val = pci_get_word(config); 895 pci_set_word(config, val | mask); 896 return val & mask; 897 } 898 899 static inline uint32_t 900 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 901 { 902 uint32_t val = pci_get_long(config); 903 pci_set_long(config, val & ~mask); 904 return val & mask; 905 } 906 907 static inline uint32_t 908 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 909 { 910 uint32_t val = pci_get_long(config); 911 pci_set_long(config, val | mask); 912 return val & mask; 913 } 914 915 static inline uint64_t 916 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 917 { 918 uint64_t val = pci_get_quad(config); 919 pci_set_quad(config, val & ~mask); 920 return val & mask; 921 } 922 923 static inline uint64_t 924 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 925 { 926 uint64_t val = pci_get_quad(config); 927 pci_set_quad(config, val | mask); 928 return val & mask; 929 } 930 931 /* Access a register specified by a mask */ 932 static inline void 933 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 934 { 935 uint8_t val = pci_get_byte(config); 936 uint8_t rval; 937 938 assert(mask); 939 rval = reg << ctz32(mask); 940 pci_set_byte(config, (~mask & val) | (mask & rval)); 941 } 942 943 static inline void 944 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 945 { 946 uint16_t val = pci_get_word(config); 947 uint16_t rval; 948 949 assert(mask); 950 rval = reg << ctz32(mask); 951 pci_set_word(config, (~mask & val) | (mask & rval)); 952 } 953 954 static inline void 955 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 956 { 957 uint32_t val = pci_get_long(config); 958 uint32_t rval; 959 960 assert(mask); 961 rval = reg << ctz32(mask); 962 pci_set_long(config, (~mask & val) | (mask & rval)); 963 } 964 965 static inline void 966 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 967 { 968 uint64_t val = pci_get_quad(config); 969 uint64_t rval; 970 971 assert(mask); 972 rval = reg << ctz32(mask); 973 pci_set_quad(config, (~mask & val) | (mask & rval)); 974 } 975 976 PCIDevice *pci_new_multifunction(int devfn, const char *name); 977 PCIDevice *pci_new(int devfn, const char *name); 978 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 979 980 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 981 const char *name); 982 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 983 984 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 985 986 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 987 void pci_set_irq(PCIDevice *pci_dev, int level); 988 int pci_irq_disabled(PCIDevice *d); 989 990 static inline void pci_irq_assert(PCIDevice *pci_dev) 991 { 992 pci_set_irq(pci_dev, 1); 993 } 994 995 static inline void pci_irq_deassert(PCIDevice *pci_dev) 996 { 997 pci_set_irq(pci_dev, 0); 998 } 999 1000 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 1001 void pci_set_enabled(PCIDevice *pci_dev, bool state); 1002 void pci_set_power(PCIDevice *pci_dev, bool state); 1003 int pci_pm_init(PCIDevice *pci_dev, uint8_t offset, Error **errp); 1004 1005 #endif 1006