1 /* 2 * QEMU SPAPR PCI BUS definitions 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #if !defined(__HW_SPAPR_H__) 20 #error Please include spapr.h before this file! 21 #endif 22 23 #if !defined(__HW_SPAPR_PCI_H__) 24 #define __HW_SPAPR_PCI_H__ 25 26 #include "hw/pci/pci.h" 27 #include "hw/pci/pci_host.h" 28 #include "hw/ppc/xics.h" 29 30 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" 31 32 #define SPAPR_PCI_HOST_BRIDGE(obj) \ 33 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 34 35 #define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \ 36 OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE) 37 #define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \ 38 OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 39 40 typedef struct sPAPRPHBClass sPAPRPHBClass; 41 typedef struct sPAPRPHBState sPAPRPHBState; 42 43 struct sPAPRPHBClass { 44 PCIHostBridgeClass parent_class; 45 46 void (*finish_realize)(sPAPRPHBState *sphb, Error **errp); 47 }; 48 49 typedef struct spapr_pci_msi { 50 uint32_t first_irq; 51 uint32_t num; 52 } spapr_pci_msi; 53 54 typedef struct spapr_pci_msi_mig { 55 uint32_t key; 56 spapr_pci_msi value; 57 } spapr_pci_msi_mig; 58 59 struct sPAPRPHBState { 60 PCIHostState parent_obj; 61 62 uint32_t index; 63 uint64_t buid; 64 char *dtbusname; 65 bool dr_enabled; 66 67 MemoryRegion memspace, iospace; 68 hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size; 69 MemoryRegion memwindow, iowindow, msiwindow; 70 71 uint32_t dma_liobn; 72 hwaddr dma_win_addr, dma_win_size; 73 AddressSpace iommu_as; 74 MemoryRegion iommu_root; 75 76 struct spapr_pci_lsi { 77 uint32_t irq; 78 } lsi_table[PCI_NUM_PINS]; 79 80 GHashTable *msi; 81 /* Temporary cache for migration purposes */ 82 int32_t msi_devs_num; 83 spapr_pci_msi_mig *msi_devs; 84 85 QLIST_ENTRY(sPAPRPHBState) list; 86 }; 87 88 #define SPAPR_PCI_MAX_INDEX 255 89 90 #define SPAPR_PCI_BASE_BUID 0x800000020000000ULL 91 92 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL 93 94 #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL 95 #define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL 96 #define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 97 #define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \ 98 SPAPR_PCI_MEM_WIN_BUS_OFFSET) 99 #define SPAPR_PCI_IO_WIN_OFF 0x80000000 100 #define SPAPR_PCI_IO_WIN_SIZE 0x10000 101 102 #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL 103 104 static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) 105 { 106 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 107 108 return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq); 109 } 110 111 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index); 112 113 int spapr_populate_pci_dt(sPAPRPHBState *phb, 114 uint32_t xics_phandle, 115 void *fdt); 116 117 void spapr_pci_msi_init(sPAPRMachineState *spapr, hwaddr addr); 118 119 void spapr_pci_rtas_init(void); 120 121 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid); 122 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 123 uint32_t config_addr); 124 125 /* VFIO EEH hooks */ 126 #ifdef CONFIG_LINUX 127 bool spapr_phb_eeh_available(sPAPRPHBState *sphb); 128 int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb, 129 unsigned int addr, int option); 130 int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state); 131 int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option); 132 int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb); 133 void spapr_phb_vfio_reset(DeviceState *qdev); 134 #else 135 static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb) 136 { 137 return false; 138 } 139 static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb, 140 unsigned int addr, int option) 141 { 142 return RTAS_OUT_HW_ERROR; 143 } 144 static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, 145 int *state) 146 { 147 return RTAS_OUT_HW_ERROR; 148 } 149 static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option) 150 { 151 return RTAS_OUT_HW_ERROR; 152 } 153 static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb) 154 { 155 return RTAS_OUT_HW_ERROR; 156 } 157 static inline void spapr_phb_vfio_reset(DeviceState *qdev) 158 { 159 } 160 #endif 161 162 #endif /* __HW_SPAPR_PCI_H__ */ 163