13384f95cSDavid Gibson /* 23384f95cSDavid Gibson * QEMU SPAPR PCI BUS definitions 33384f95cSDavid Gibson * 43384f95cSDavid Gibson * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> 53384f95cSDavid Gibson * 63384f95cSDavid Gibson * This library is free software; you can redistribute it and/or 73384f95cSDavid Gibson * modify it under the terms of the GNU Lesser General Public 83384f95cSDavid Gibson * License as published by the Free Software Foundation; either 93384f95cSDavid Gibson * version 2 of the License, or (at your option) any later version. 103384f95cSDavid Gibson * 113384f95cSDavid Gibson * This library is distributed in the hope that it will be useful, 123384f95cSDavid Gibson * but WITHOUT ANY WARRANTY; without even the implied warranty of 133384f95cSDavid Gibson * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 143384f95cSDavid Gibson * Lesser General Public License for more details. 153384f95cSDavid Gibson * 163384f95cSDavid Gibson * You should have received a copy of the GNU Lesser General Public 173384f95cSDavid Gibson * License along with this library; if not, see <http://www.gnu.org/licenses/>. 183384f95cSDavid Gibson */ 193384f95cSDavid Gibson #if !defined(__HW_SPAPR_H__) 203384f95cSDavid Gibson #error Please include spapr.h before this file! 213384f95cSDavid Gibson #endif 223384f95cSDavid Gibson 233384f95cSDavid Gibson #if !defined(__HW_SPAPR_PCI_H__) 243384f95cSDavid Gibson #define __HW_SPAPR_PCI_H__ 253384f95cSDavid Gibson 26a2cb15b0SMichael S. Tsirkin #include "hw/pci/pci.h" 27a2cb15b0SMichael S. Tsirkin #include "hw/pci/pci_host.h" 280d09e41aSPaolo Bonzini #include "hw/ppc/xics.h" 293384f95cSDavid Gibson 308c9f64dfSAndreas Färber #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" 319fc34adaSAlexey Kardashevskiy #define TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE "spapr-pci-vfio-host-bridge" 328c9f64dfSAndreas Färber 338c9f64dfSAndreas Färber #define SPAPR_PCI_HOST_BRIDGE(obj) \ 348c9f64dfSAndreas Färber OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 358c9f64dfSAndreas Färber 369fc34adaSAlexey Kardashevskiy #define SPAPR_PCI_VFIO_HOST_BRIDGE(obj) \ 379fc34adaSAlexey Kardashevskiy OBJECT_CHECK(sPAPRPHBVFIOState, (obj), TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE) 389fc34adaSAlexey Kardashevskiy 39da6ccee4SAlexey Kardashevskiy #define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \ 40da6ccee4SAlexey Kardashevskiy OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE) 41da6ccee4SAlexey Kardashevskiy #define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \ 42da6ccee4SAlexey Kardashevskiy OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 43da6ccee4SAlexey Kardashevskiy 44da6ccee4SAlexey Kardashevskiy typedef struct sPAPRPHBClass sPAPRPHBClass; 45da6ccee4SAlexey Kardashevskiy typedef struct sPAPRPHBState sPAPRPHBState; 469fc34adaSAlexey Kardashevskiy typedef struct sPAPRPHBVFIOState sPAPRPHBVFIOState; 47da6ccee4SAlexey Kardashevskiy 48da6ccee4SAlexey Kardashevskiy struct sPAPRPHBClass { 49da6ccee4SAlexey Kardashevskiy PCIHostBridgeClass parent_class; 50da6ccee4SAlexey Kardashevskiy 51da6ccee4SAlexey Kardashevskiy void (*finish_realize)(sPAPRPHBState *sphb, Error **errp); 52ee954280SGavin Shan int (*eeh_set_option)(sPAPRPHBState *sphb, unsigned int addr, int option); 53ee954280SGavin Shan int (*eeh_get_state)(sPAPRPHBState *sphb, int *state); 54ee954280SGavin Shan int (*eeh_reset)(sPAPRPHBState *sphb, int option); 55ee954280SGavin Shan int (*eeh_configure)(sPAPRPHBState *sphb); 56da6ccee4SAlexey Kardashevskiy }; 57da6ccee4SAlexey Kardashevskiy 589a321e92SAlexey Kardashevskiy typedef struct spapr_pci_msi { 599a321e92SAlexey Kardashevskiy uint32_t first_irq; 609a321e92SAlexey Kardashevskiy uint32_t num; 619a321e92SAlexey Kardashevskiy } spapr_pci_msi; 629a321e92SAlexey Kardashevskiy 639a321e92SAlexey Kardashevskiy typedef struct spapr_pci_msi_mig { 649a321e92SAlexey Kardashevskiy uint32_t key; 659a321e92SAlexey Kardashevskiy spapr_pci_msi value; 669a321e92SAlexey Kardashevskiy } spapr_pci_msi_mig; 679a321e92SAlexey Kardashevskiy 68da6ccee4SAlexey Kardashevskiy struct sPAPRPHBState { 6967c332fdSAndreas Färber PCIHostState parent_obj; 703384f95cSDavid Gibson 713e4ac968SDavid Gibson uint32_t index; 723384f95cSDavid Gibson uint64_t buid; 73298a9710SDavid Gibson char *dtbusname; 747619c7b0SMichael Roth bool dr_enabled; 753384f95cSDavid Gibson 763384f95cSDavid Gibson MemoryRegion memspace, iospace; 77a8170e5eSAvi Kivity hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size; 788c46f7ecSGreg Kurz MemoryRegion memwindow, iowindow, msiwindow; 790ee2c058SAlexey Kardashevskiy 805c4cbcf2SAlexey Kardashevskiy uint32_t dma_liobn; 81*f93caaacSDavid Gibson hwaddr dma_win_addr, dma_win_size; 82e00387d5SAvi Kivity AddressSpace iommu_as; 83cca7fad5SAlexey Kardashevskiy MemoryRegion iommu_root; 843384f95cSDavid Gibson 851112cf94SDavid Gibson struct spapr_pci_lsi { 86a307d594SAlexey Kardashevskiy uint32_t irq; 877fb0bd34SDavid Gibson } lsi_table[PCI_NUM_PINS]; 883384f95cSDavid Gibson 899a321e92SAlexey Kardashevskiy GHashTable *msi; 909a321e92SAlexey Kardashevskiy /* Temporary cache for migration purposes */ 919a321e92SAlexey Kardashevskiy int32_t msi_devs_num; 929a321e92SAlexey Kardashevskiy spapr_pci_msi_mig *msi_devs; 930ee2c058SAlexey Kardashevskiy 943384f95cSDavid Gibson QLIST_ENTRY(sPAPRPHBState) list; 95da6ccee4SAlexey Kardashevskiy }; 963384f95cSDavid Gibson 979fc34adaSAlexey Kardashevskiy struct sPAPRPHBVFIOState { 989fc34adaSAlexey Kardashevskiy sPAPRPHBState phb; 999fc34adaSAlexey Kardashevskiy 1009fc34adaSAlexey Kardashevskiy int32_t iommugroupid; 1019fc34adaSAlexey Kardashevskiy }; 1029fc34adaSAlexey Kardashevskiy 1033e4ac968SDavid Gibson #define SPAPR_PCI_MAX_INDEX 255 1043e4ac968SDavid Gibson 105caae58cbSDavid Gibson #define SPAPR_PCI_BASE_BUID 0x800000020000000ULL 106caae58cbSDavid Gibson 107b194df47SAlexey Kardashevskiy #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL 108b194df47SAlexey Kardashevskiy 109caae58cbSDavid Gibson #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL 110caae58cbSDavid Gibson #define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL 111caae58cbSDavid Gibson #define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 112b194df47SAlexey Kardashevskiy #define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \ 113b194df47SAlexey Kardashevskiy SPAPR_PCI_MEM_WIN_BUS_OFFSET) 114caae58cbSDavid Gibson #define SPAPR_PCI_IO_WIN_OFF 0x80000000 115caae58cbSDavid Gibson #define SPAPR_PCI_IO_WIN_SIZE 0x10000 116f1c2dc7cSAlexey Kardashevskiy 117f1c2dc7cSAlexey Kardashevskiy #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL 118caae58cbSDavid Gibson 119a307d594SAlexey Kardashevskiy static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) 120a307d594SAlexey Kardashevskiy { 12128e02042SDavid Gibson sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 12228e02042SDavid Gibson 123a307d594SAlexey Kardashevskiy return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq); 124a307d594SAlexey Kardashevskiy } 125a307d594SAlexey Kardashevskiy 12628e02042SDavid Gibson PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index); 1273384f95cSDavid Gibson 128e0fdbd7cSAlexey Kardashevskiy int spapr_populate_pci_dt(sPAPRPHBState *phb, 1293384f95cSDavid Gibson uint32_t xics_phandle, 1303384f95cSDavid Gibson void *fdt); 1313384f95cSDavid Gibson 13228e02042SDavid Gibson void spapr_pci_msi_init(sPAPRMachineState *spapr, hwaddr addr); 133f1c2dc7cSAlexey Kardashevskiy 134fa28f71bSAlexey Kardashevskiy void spapr_pci_rtas_init(void); 135fa28f71bSAlexey Kardashevskiy 13628e02042SDavid Gibson sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid); 13728e02042SDavid Gibson PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 13846c5874eSAlexey Kardashevskiy uint32_t config_addr); 13946c5874eSAlexey Kardashevskiy 1403384f95cSDavid Gibson #endif /* __HW_SPAPR_PCI_H__ */ 141