1 #ifndef PCI_HOST_APB_H 2 #define PCI_HOST_APB_H 3 4 #include "hw/sparc/sun4u_iommu.h" 5 6 #define MAX_IVEC 0x40 7 8 /* OBIO IVEC IRQs */ 9 #define OBIO_HDD_IRQ 0x20 10 #define OBIO_NIC_IRQ 0x21 11 #define OBIO_LPT_IRQ 0x22 12 #define OBIO_FDD_IRQ 0x27 13 #define OBIO_KBD_IRQ 0x29 14 #define OBIO_MSE_IRQ 0x2a 15 #define OBIO_SER_IRQ 0x2b 16 17 #define TYPE_APB "pbm" 18 19 #define APB_DEVICE(obj) \ 20 OBJECT_CHECK(APBState, (obj), TYPE_APB) 21 22 typedef struct APBState { 23 PCIHostState parent_obj; 24 25 hwaddr special_base; 26 hwaddr mem_base; 27 MemoryRegion apb_config; 28 MemoryRegion pci_config; 29 MemoryRegion pci_mmio; 30 MemoryRegion pci_ioport; 31 uint64_t pci_irq_in; 32 IOMMUState *iommu; 33 PCIBridge *bridgeA; 34 PCIBridge *bridgeB; 35 uint32_t pci_control[16]; 36 uint32_t pci_irq_map[8]; 37 uint32_t pci_err_irq_map[4]; 38 uint32_t obio_irq_map[32]; 39 qemu_irq ivec_irqs[MAX_IVEC]; 40 unsigned int irq_request; 41 uint32_t reset_control; 42 unsigned int nr_resets; 43 } APBState; 44 45 #endif 46