1 /* 2 * q35.h 3 * 4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/> 20 */ 21 22 #ifndef HW_Q35_H 23 #define HW_Q35_H 24 25 #include "hw/isa/isa.h" 26 #include "hw/sysbus.h" 27 #include "hw/i386/pc.h" 28 #include "hw/isa/apm.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pcie_host.h" 31 #include "hw/acpi/acpi.h" 32 #include "hw/acpi/ich9.h" 33 #include "hw/pci-host/pam.h" 34 #include "hw/i386/intel_iommu.h" 35 #include "qemu/units.h" 36 #include "qemu/range.h" 37 38 #define TYPE_Q35_HOST_DEVICE "q35-pcihost" 39 #define Q35_HOST_DEVICE(obj) \ 40 OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE) 41 42 #define TYPE_MCH_PCI_DEVICE "mch" 43 #define MCH_PCI_DEVICE(obj) \ 44 OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE) 45 46 typedef struct MCHPCIState { 47 /*< private >*/ 48 PCIDevice parent_obj; 49 /*< public >*/ 50 51 MemoryRegion *ram_memory; 52 MemoryRegion *pci_address_space; 53 MemoryRegion *system_memory; 54 MemoryRegion *address_space_io; 55 PAMMemoryRegion pam_regions[13]; 56 MemoryRegion smram_region, open_high_smram; 57 MemoryRegion smram, low_smram, high_smram; 58 MemoryRegion tseg_blackhole, tseg_window; 59 MemoryRegion smbase_blackhole, smbase_window; 60 bool has_smram_at_smbase; 61 Range pci_hole; 62 uint64_t below_4g_mem_size; 63 uint64_t above_4g_mem_size; 64 uint64_t pci_hole64_size; 65 uint32_t short_root_bus; 66 uint16_t ext_tseg_mbytes; 67 } MCHPCIState; 68 69 typedef struct Q35PCIHost { 70 /*< private >*/ 71 PCIExpressHost parent_obj; 72 /*< public >*/ 73 74 bool pci_hole64_fix; 75 MCHPCIState mch; 76 } Q35PCIHost; 77 78 #define Q35_MASK(bit, ms_bit, ls_bit) \ 79 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 80 81 /* 82 * gmch part 83 */ 84 85 #define MCH_HOST_PROP_RAM_MEM "ram-mem" 86 #define MCH_HOST_PROP_PCI_MEM "pci-mem" 87 #define MCH_HOST_PROP_SYSTEM_MEM "system-mem" 88 #define MCH_HOST_PROP_IO_MEM "io-mem" 89 90 /* PCI configuration */ 91 #define MCH_HOST_BRIDGE "MCH" 92 93 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8 94 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc 95 96 /* D0:F0 configuration space */ 97 #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0 98 99 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50 100 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE 2 101 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff 102 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff 103 104 #define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB) 105 #define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000 106 #define MCH_HOST_BRIDGE_F_SMBASE 0x9c 107 #define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff 108 #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01 109 #define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02 110 111 #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */ 112 #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */ 113 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 114 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ 115 #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) 116 #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) 117 #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) 118 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1)) 119 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1)) 120 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1)) 121 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1)) 122 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1)) 123 #define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1) 124 125 #define MCH_HOST_BRIDGE_PAM_NB 7 126 #define MCH_HOST_BRIDGE_PAM_SIZE 7 127 #define MCH_HOST_BRIDGE_PAM0 0x90 128 #define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000 129 #define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */ 130 #define MCH_HOST_BRIDGE_PAM1 0x91 131 #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000 132 #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000 133 #define MCH_HOST_BRIDGE_PAM2 0x92 134 #define MCH_HOST_BRIDGE_PAM3 0x93 135 #define MCH_HOST_BRIDGE_PAM4 0x94 136 #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000 137 #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000 138 #define MCH_HOST_BRIDGE_PAM5 0x95 139 #define MCH_HOST_BRIDGE_PAM6 0x96 140 #define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4)) 141 #define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4)) 142 #define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4)) 143 #define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2) 144 #define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1) 145 #define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3) 146 #define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2) 147 #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1) 148 #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3) 149 150 #define MCH_HOST_BRIDGE_SMRAM 0x9d 151 #define MCH_HOST_BRIDGE_SMRAM_SIZE 2 152 #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6)) 153 #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5)) 154 #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4)) 155 #define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3)) 156 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7) 157 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */ 158 #define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000 159 #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000 160 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000 161 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 162 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ 163 MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG 164 #define MCH_HOST_BRIDGE_SMRAM_WMASK \ 165 (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \ 166 MCH_HOST_BRIDGE_SMRAM_D_CLS | \ 167 MCH_HOST_BRIDGE_SMRAM_D_LCK | \ 168 MCH_HOST_BRIDGE_SMRAM_G_SMRAME) 169 #define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \ 170 MCH_HOST_BRIDGE_SMRAM_D_CLS 171 172 #define MCH_HOST_BRIDGE_ESMRAMC 0x9e 173 #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) 174 #define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 6)) 175 #define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 5)) 176 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 4)) 177 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 3)) 178 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1)) 179 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1)) 180 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1)) 181 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1)) 182 #define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1) 183 #define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \ 184 (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ 185 MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ 186 MCH_HOST_BRIDGE_ESMRAMC_SM_L2) 187 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK \ 188 (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \ 189 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \ 190 MCH_HOST_BRIDGE_ESMRAMC_T_EN) 191 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0 192 193 /* D1:F0 PCIE* port*/ 194 #define MCH_PCIE_DEV 1 195 #define MCH_PCIE_FUNC 0 196 197 uint64_t mch_mcfg_base(void); 198 199 /* 200 * Arbitrary but unique BNF number for IOAPIC device. 201 * 202 * TODO: make sure there would have no conflict with real PCI bus 203 */ 204 #define Q35_PSEUDO_BUS_PLATFORM (0xff) 205 #define Q35_PSEUDO_DEVFN_IOAPIC (0x00) 206 207 #endif /* HW_Q35_H */ 208