xref: /qemu/include/hw/net/xlnx-versal-canfd.h (revision f5e6786de4815751b0a3d2235c760361f228ea48)
1*32dbebccSVikram Garhwal /*
2*32dbebccSVikram Garhwal  * QEMU model of the Xilinx Versal CANFD Controller.
3*32dbebccSVikram Garhwal  *
4*32dbebccSVikram Garhwal  * Copyright (c) 2023 Advanced Micro Devices, Inc.
5*32dbebccSVikram Garhwal  *
6*32dbebccSVikram Garhwal  * Written-by: Vikram Garhwal<vikram.garhwal@amd.com>
7*32dbebccSVikram Garhwal  * Based on QEMU CANFD Device emulation implemented by Jin Yang, Deniz Eren and
8*32dbebccSVikram Garhwal  * Pavel Pisa.
9*32dbebccSVikram Garhwal  * Permission is hereby granted, free of charge, to any person obtaining a copy
10*32dbebccSVikram Garhwal  * of this software and associated documentation files (the "Software"), to deal
11*32dbebccSVikram Garhwal  * in the Software without restriction, including without limitation the rights
12*32dbebccSVikram Garhwal  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13*32dbebccSVikram Garhwal  * copies of the Software, and to permit persons to whom the Software is
14*32dbebccSVikram Garhwal  * furnished to do so, subject to the following conditions:
15*32dbebccSVikram Garhwal  *
16*32dbebccSVikram Garhwal  * The above copyright notice and this permission notice shall be included in
17*32dbebccSVikram Garhwal  * all copies or substantial portions of the Software.
18*32dbebccSVikram Garhwal  *
19*32dbebccSVikram Garhwal  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20*32dbebccSVikram Garhwal  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21*32dbebccSVikram Garhwal  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22*32dbebccSVikram Garhwal  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23*32dbebccSVikram Garhwal  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24*32dbebccSVikram Garhwal  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25*32dbebccSVikram Garhwal  * THE SOFTWARE.
26*32dbebccSVikram Garhwal  */
27*32dbebccSVikram Garhwal 
28*32dbebccSVikram Garhwal #ifndef HW_CANFD_XILINX_H
29*32dbebccSVikram Garhwal #define HW_CANFD_XILINX_H
30*32dbebccSVikram Garhwal 
31*32dbebccSVikram Garhwal #include "hw/register.h"
32*32dbebccSVikram Garhwal #include "hw/ptimer.h"
33*32dbebccSVikram Garhwal #include "net/can_emu.h"
34*32dbebccSVikram Garhwal #include "hw/qdev-clock.h"
35*32dbebccSVikram Garhwal 
36*32dbebccSVikram Garhwal #define TYPE_XILINX_CANFD "xlnx.versal-canfd"
37*32dbebccSVikram Garhwal 
38*32dbebccSVikram Garhwal OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCANFDState, XILINX_CANFD)
39*32dbebccSVikram Garhwal 
40*32dbebccSVikram Garhwal #define NUM_REGS_PER_MSG_SPACE 18 /* 1 ID + 1 DLC + 16 Data(DW0 - DW15) regs. */
41*32dbebccSVikram Garhwal #define MAX_NUM_RX             64
42*32dbebccSVikram Garhwal #define OFFSET_RX1_DW15        (0x4144 / 4)
43*32dbebccSVikram Garhwal #define CANFD_TIMER_MAX        0xFFFFUL
44*32dbebccSVikram Garhwal #define CANFD_DEFAULT_CLOCK    (25 * 1000 * 1000)
45*32dbebccSVikram Garhwal 
46*32dbebccSVikram Garhwal #define XLNX_VERSAL_CANFD_R_MAX (OFFSET_RX1_DW15 + \
47*32dbebccSVikram Garhwal                     ((MAX_NUM_RX - 1) * NUM_REGS_PER_MSG_SPACE) + 1)
48*32dbebccSVikram Garhwal 
49*32dbebccSVikram Garhwal typedef struct XlnxVersalCANFDState {
50*32dbebccSVikram Garhwal     SysBusDevice            parent_obj;
51*32dbebccSVikram Garhwal     MemoryRegion            iomem;
52*32dbebccSVikram Garhwal 
53*32dbebccSVikram Garhwal     qemu_irq                irq_canfd_int;
54*32dbebccSVikram Garhwal     qemu_irq                irq_addr_err;
55*32dbebccSVikram Garhwal 
56*32dbebccSVikram Garhwal     RegisterInfo            reg_info[XLNX_VERSAL_CANFD_R_MAX];
57*32dbebccSVikram Garhwal     RegisterAccessInfo      *tx_regs;
58*32dbebccSVikram Garhwal     RegisterAccessInfo      *rx0_regs;
59*32dbebccSVikram Garhwal     RegisterAccessInfo      *rx1_regs;
60*32dbebccSVikram Garhwal     RegisterAccessInfo      *af_regs;
61*32dbebccSVikram Garhwal     RegisterAccessInfo      *txe_regs;
62*32dbebccSVikram Garhwal     RegisterAccessInfo      *rx_mailbox_regs;
63*32dbebccSVikram Garhwal     RegisterAccessInfo      *af_mask_regs_mailbox;
64*32dbebccSVikram Garhwal 
65*32dbebccSVikram Garhwal     uint32_t                regs[XLNX_VERSAL_CANFD_R_MAX];
66*32dbebccSVikram Garhwal 
67*32dbebccSVikram Garhwal     ptimer_state            *canfd_timer;
68*32dbebccSVikram Garhwal 
69*32dbebccSVikram Garhwal     CanBusClientState       bus_client;
70*32dbebccSVikram Garhwal     CanBusState             *canfdbus;
71*32dbebccSVikram Garhwal 
72*32dbebccSVikram Garhwal     struct {
73*32dbebccSVikram Garhwal         uint8_t             rx0_fifo;
74*32dbebccSVikram Garhwal         uint8_t             rx1_fifo;
75*32dbebccSVikram Garhwal         uint8_t             tx_fifo;
76*32dbebccSVikram Garhwal         bool                enable_rx_fifo1;
77*32dbebccSVikram Garhwal         uint32_t            ext_clk_freq;
78*32dbebccSVikram Garhwal    } cfg;
79*32dbebccSVikram Garhwal 
80*32dbebccSVikram Garhwal } XlnxVersalCANFDState;
81*32dbebccSVikram Garhwal 
82*32dbebccSVikram Garhwal typedef struct tx_ready_reg_info {
83*32dbebccSVikram Garhwal     uint32_t can_id;
84*32dbebccSVikram Garhwal     uint32_t reg_num;
85*32dbebccSVikram Garhwal } tx_ready_reg_info;
86*32dbebccSVikram Garhwal 
87*32dbebccSVikram Garhwal #endif
88