xref: /qemu/include/hw/net/npcm_pcs.h (revision 96adf9b404e51b9acdf9592595ad935905de1f4e)
1 /*
2  * Nuvoton NPCM8xx PCS Module
3  *
4  * Copyright 2022 Google LLC
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the
8  * Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14  * for more details.
15  */
16 
17 #ifndef NPCM_PCS_H
18 #define NPCM_PCS_H
19 
20 #include "hw/sysbus.h"
21 
22 #define NPCM_PCS_NR_SR_CTLS     (0x12 / sizeof(uint16_t))
23 #define NPCM_PCS_NR_SR_MIIS     (0x20 / sizeof(uint16_t))
24 #define NPCM_PCS_NR_SR_TIMS     (0x22 / sizeof(uint16_t))
25 #define NPCM_PCS_NR_VR_MIIS     (0x1c6 / sizeof(uint16_t))
26 
27 struct NPCMPCSState {
28     SysBusDevice parent;
29 
30     MemoryRegion iomem;
31 
32     uint16_t indirect_access_base;
33     uint16_t sr_ctl[NPCM_PCS_NR_SR_CTLS];
34     uint16_t sr_mii[NPCM_PCS_NR_SR_MIIS];
35     uint16_t sr_tim[NPCM_PCS_NR_SR_TIMS];
36     uint16_t vr_mii[NPCM_PCS_NR_VR_MIIS];
37 };
38 
39 #define TYPE_NPCM_PCS "npcm-pcs"
40 OBJECT_DECLARE_SIMPLE_TYPE(NPCMPCSState, NPCM_PCS)
41 
42 #endif /* NPCM_PCS_H */
43