1*3d107d36SHao Wu /* 2*3d107d36SHao Wu * Nuvoton NPCM8xx PCS Module 3*3d107d36SHao Wu * 4*3d107d36SHao Wu * Copyright 2022 Google LLC 5*3d107d36SHao Wu * 6*3d107d36SHao Wu * This program is free software; you can redistribute it and/or modify it 7*3d107d36SHao Wu * under the terms of the GNU General Public License as published by the 8*3d107d36SHao Wu * Free Software Foundation; either version 2 of the License, or 9*3d107d36SHao Wu * (at your option) any later version. 10*3d107d36SHao Wu * 11*3d107d36SHao Wu * This program is distributed in the hope that it will be useful, but WITHOUT 12*3d107d36SHao Wu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13*3d107d36SHao Wu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14*3d107d36SHao Wu * for more details. 15*3d107d36SHao Wu */ 16*3d107d36SHao Wu 17*3d107d36SHao Wu #ifndef NPCM_PCS_H 18*3d107d36SHao Wu #define NPCM_PCS_H 19*3d107d36SHao Wu 20*3d107d36SHao Wu #include "hw/sysbus.h" 21*3d107d36SHao Wu 22*3d107d36SHao Wu #define NPCM_PCS_NR_SR_CTLS (0x12 / sizeof(uint16_t)) 23*3d107d36SHao Wu #define NPCM_PCS_NR_SR_MIIS (0x20 / sizeof(uint16_t)) 24*3d107d36SHao Wu #define NPCM_PCS_NR_SR_TIMS (0x22 / sizeof(uint16_t)) 25*3d107d36SHao Wu #define NPCM_PCS_NR_VR_MIIS (0x1c6 / sizeof(uint16_t)) 26*3d107d36SHao Wu 27*3d107d36SHao Wu struct NPCMPCSState { 28*3d107d36SHao Wu SysBusDevice parent; 29*3d107d36SHao Wu 30*3d107d36SHao Wu MemoryRegion iomem; 31*3d107d36SHao Wu 32*3d107d36SHao Wu uint16_t indirect_access_base; 33*3d107d36SHao Wu uint16_t sr_ctl[NPCM_PCS_NR_SR_CTLS]; 34*3d107d36SHao Wu uint16_t sr_mii[NPCM_PCS_NR_SR_MIIS]; 35*3d107d36SHao Wu uint16_t sr_tim[NPCM_PCS_NR_SR_TIMS]; 36*3d107d36SHao Wu uint16_t vr_mii[NPCM_PCS_NR_VR_MIIS]; 37*3d107d36SHao Wu }; 38*3d107d36SHao Wu 39*3d107d36SHao Wu #define TYPE_NPCM_PCS "npcm-pcs" 40*3d107d36SHao Wu OBJECT_DECLARE_SIMPLE_TYPE(NPCMPCSState, NPCM_PCS) 41*3d107d36SHao Wu 42*3d107d36SHao Wu #endif /* NPCM_PCS_H */ 43