1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * Copyright (C) 2016-2017, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef FTGMAC100_H 11 #define FTGMAC100_H 12 #include "qom/object.h" 13 14 #define TYPE_FTGMAC100 "ftgmac100" 15 OBJECT_DECLARE_SIMPLE_TYPE(FTGMAC100State, FTGMAC100) 16 17 #define FTGMAC100_MEM_SIZE 0x1000 18 #define FTGMAC100_REG_MEM_SIZE 0x100 19 20 #include "hw/sysbus.h" 21 #include "net/net.h" 22 23 /* 24 * Max frame size for the receiving buffer 25 */ 26 #define FTGMAC100_MAX_FRAME_SIZE 9220 27 28 struct FTGMAC100State { 29 /*< private >*/ 30 SysBusDevice parent_obj; 31 32 /*< public >*/ 33 NICState *nic; 34 NICConf conf; 35 qemu_irq irq; 36 MemoryRegion iomem_container; 37 MemoryRegion iomem; 38 39 uint8_t frame[FTGMAC100_MAX_FRAME_SIZE]; 40 41 uint32_t irq_state; 42 uint32_t isr; 43 uint32_t ier; 44 uint32_t rx_enabled; 45 uint32_t rx_ring; 46 uint32_t rx_descriptor; 47 uint32_t tx_ring; 48 uint32_t tx_descriptor; 49 uint32_t math[2]; 50 uint32_t rbsr; 51 uint32_t itc; 52 uint32_t aptcr; 53 uint32_t dblac; 54 uint32_t revr; 55 uint32_t fear1; 56 uint32_t tpafcr; 57 uint32_t maccr; 58 uint32_t phycr; 59 uint32_t phydata; 60 uint32_t fcr; 61 62 63 uint32_t phy_status; 64 uint32_t phy_control; 65 uint32_t phy_advertise; 66 uint32_t phy_int; 67 uint32_t phy_int_mask; 68 69 bool aspeed; 70 uint32_t txdes0_edotr; 71 uint32_t rxdes0_edorr; 72 }; 73 74 #define TYPE_ASPEED_MII "aspeed-mmi" 75 OBJECT_DECLARE_SIMPLE_TYPE(AspeedMiiState, ASPEED_MII) 76 77 /* 78 * AST2600 MII controller 79 */ 80 struct AspeedMiiState { 81 /*< private >*/ 82 SysBusDevice parent_obj; 83 84 FTGMAC100State *nic; 85 86 MemoryRegion iomem; 87 uint32_t phycr; 88 uint32_t phydata; 89 }; 90 91 #endif 92