1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef CADENCE_GEM_H 26 27 #define TYPE_CADENCE_GEM "cadence_gem" 28 #define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM) 29 30 #include "net/net.h" 31 #include "hw/sysbus.h" 32 33 #define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ 34 35 #define MAX_PRIORITY_QUEUES 8 36 37 typedef struct CadenceGEMState { 38 /*< private >*/ 39 SysBusDevice parent_obj; 40 41 /*< public >*/ 42 MemoryRegion iomem; 43 NICState *nic; 44 NICConf conf; 45 qemu_irq irq[MAX_PRIORITY_QUEUES]; 46 47 /* Static properties */ 48 uint8_t num_priority_queues; 49 50 /* GEM registers backing store */ 51 uint32_t regs[CADENCE_GEM_MAXREG]; 52 /* Mask of register bits which are write only */ 53 uint32_t regs_wo[CADENCE_GEM_MAXREG]; 54 /* Mask of register bits which are read only */ 55 uint32_t regs_ro[CADENCE_GEM_MAXREG]; 56 /* Mask of register bits which are clear on read */ 57 uint32_t regs_rtc[CADENCE_GEM_MAXREG]; 58 /* Mask of register bits which are write 1 to clear */ 59 uint32_t regs_w1c[CADENCE_GEM_MAXREG]; 60 61 /* PHY registers backing store */ 62 uint16_t phy_regs[32]; 63 64 uint8_t phy_loop; /* Are we in phy loopback? */ 65 66 /* The current DMA descriptor pointers */ 67 uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES]; 68 uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES]; 69 70 uint8_t can_rx_state; /* Debug only */ 71 72 unsigned rx_desc[MAX_PRIORITY_QUEUES][2]; 73 74 bool sar_active[4]; 75 } CadenceGEMState; 76 77 #define CADENCE_GEM_H 78 #endif 79