1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef CADENCE_GEM_H 26 #define CADENCE_GEM_H 27 28 #define TYPE_CADENCE_GEM "cadence_gem" 29 #define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM) 30 31 #include "net/net.h" 32 #include "hw/sysbus.h" 33 34 #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ 35 36 /* Max number of words in a DMA descriptor. */ 37 #define DESC_MAX_NUM_WORDS 6 38 39 #define MAX_PRIORITY_QUEUES 8 40 #define MAX_TYPE1_SCREENERS 16 41 #define MAX_TYPE2_SCREENERS 16 42 43 #define MAX_FRAME_SIZE 2048 44 45 typedef struct CadenceGEMState { 46 /*< private >*/ 47 SysBusDevice parent_obj; 48 49 /*< public >*/ 50 MemoryRegion iomem; 51 MemoryRegion *dma_mr; 52 AddressSpace dma_as; 53 NICState *nic; 54 NICConf conf; 55 qemu_irq irq[MAX_PRIORITY_QUEUES]; 56 57 /* Static properties */ 58 uint8_t num_priority_queues; 59 uint8_t num_type1_screeners; 60 uint8_t num_type2_screeners; 61 uint32_t revision; 62 63 /* GEM registers backing store */ 64 uint32_t regs[CADENCE_GEM_MAXREG]; 65 /* Mask of register bits which are write only */ 66 uint32_t regs_wo[CADENCE_GEM_MAXREG]; 67 /* Mask of register bits which are read only */ 68 uint32_t regs_ro[CADENCE_GEM_MAXREG]; 69 /* Mask of register bits which are clear on read */ 70 uint32_t regs_rtc[CADENCE_GEM_MAXREG]; 71 /* Mask of register bits which are write 1 to clear */ 72 uint32_t regs_w1c[CADENCE_GEM_MAXREG]; 73 74 /* PHY registers backing store */ 75 uint16_t phy_regs[32]; 76 77 uint8_t phy_loop; /* Are we in phy loopback? */ 78 79 /* The current DMA descriptor pointers */ 80 uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES]; 81 uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES]; 82 83 uint8_t can_rx_state; /* Debug only */ 84 85 uint8_t tx_packet[MAX_FRAME_SIZE]; 86 uint8_t rx_packet[MAX_FRAME_SIZE]; 87 uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; 88 89 bool sar_active[4]; 90 } CadenceGEMState; 91 92 #endif 93