1f49856d4SPeter Crosthwaite /* 2f49856d4SPeter Crosthwaite * QEMU Cadence GEM emulation 3f49856d4SPeter Crosthwaite * 4f49856d4SPeter Crosthwaite * Copyright (c) 2011 Xilinx, Inc. 5f49856d4SPeter Crosthwaite * 6f49856d4SPeter Crosthwaite * Permission is hereby granted, free of charge, to any person obtaining a copy 7f49856d4SPeter Crosthwaite * of this software and associated documentation files (the "Software"), to deal 8f49856d4SPeter Crosthwaite * in the Software without restriction, including without limitation the rights 9f49856d4SPeter Crosthwaite * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10f49856d4SPeter Crosthwaite * copies of the Software, and to permit persons to whom the Software is 11f49856d4SPeter Crosthwaite * furnished to do so, subject to the following conditions: 12f49856d4SPeter Crosthwaite * 13f49856d4SPeter Crosthwaite * The above copyright notice and this permission notice shall be included in 14f49856d4SPeter Crosthwaite * all copies or substantial portions of the Software. 15f49856d4SPeter Crosthwaite * 16f49856d4SPeter Crosthwaite * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17f49856d4SPeter Crosthwaite * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18f49856d4SPeter Crosthwaite * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19f49856d4SPeter Crosthwaite * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20f49856d4SPeter Crosthwaite * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21f49856d4SPeter Crosthwaite * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22f49856d4SPeter Crosthwaite * THE SOFTWARE. 23f49856d4SPeter Crosthwaite */ 24f49856d4SPeter Crosthwaite 25f49856d4SPeter Crosthwaite #ifndef CADENCE_GEM_H 26f49856d4SPeter Crosthwaite 27f49856d4SPeter Crosthwaite #define TYPE_CADENCE_GEM "cadence_gem" 28f49856d4SPeter Crosthwaite #define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM) 29f49856d4SPeter Crosthwaite 30f49856d4SPeter Crosthwaite #include "net/net.h" 31f49856d4SPeter Crosthwaite #include "hw/sysbus.h" 32f49856d4SPeter Crosthwaite 33*e8e49943SAlistair Francis #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ 34f49856d4SPeter Crosthwaite 352bf57f73SAlistair Francis #define MAX_PRIORITY_QUEUES 8 36*e8e49943SAlistair Francis #define MAX_TYPE1_SCREENERS 16 37*e8e49943SAlistair Francis #define MAX_TYPE2_SCREENERS 16 382bf57f73SAlistair Francis 39f49856d4SPeter Crosthwaite typedef struct CadenceGEMState { 40f49856d4SPeter Crosthwaite /*< private >*/ 41f49856d4SPeter Crosthwaite SysBusDevice parent_obj; 42f49856d4SPeter Crosthwaite 43f49856d4SPeter Crosthwaite /*< public >*/ 44f49856d4SPeter Crosthwaite MemoryRegion iomem; 45f49856d4SPeter Crosthwaite NICState *nic; 46f49856d4SPeter Crosthwaite NICConf conf; 472bf57f73SAlistair Francis qemu_irq irq[MAX_PRIORITY_QUEUES]; 482bf57f73SAlistair Francis 492bf57f73SAlistair Francis /* Static properties */ 502bf57f73SAlistair Francis uint8_t num_priority_queues; 51*e8e49943SAlistair Francis uint8_t num_type1_screeners; 52*e8e49943SAlistair Francis uint8_t num_type2_screeners; 53f49856d4SPeter Crosthwaite 54f49856d4SPeter Crosthwaite /* GEM registers backing store */ 55f49856d4SPeter Crosthwaite uint32_t regs[CADENCE_GEM_MAXREG]; 56f49856d4SPeter Crosthwaite /* Mask of register bits which are write only */ 57f49856d4SPeter Crosthwaite uint32_t regs_wo[CADENCE_GEM_MAXREG]; 58f49856d4SPeter Crosthwaite /* Mask of register bits which are read only */ 59f49856d4SPeter Crosthwaite uint32_t regs_ro[CADENCE_GEM_MAXREG]; 60f49856d4SPeter Crosthwaite /* Mask of register bits which are clear on read */ 61f49856d4SPeter Crosthwaite uint32_t regs_rtc[CADENCE_GEM_MAXREG]; 62f49856d4SPeter Crosthwaite /* Mask of register bits which are write 1 to clear */ 63f49856d4SPeter Crosthwaite uint32_t regs_w1c[CADENCE_GEM_MAXREG]; 64f49856d4SPeter Crosthwaite 65f49856d4SPeter Crosthwaite /* PHY registers backing store */ 66f49856d4SPeter Crosthwaite uint16_t phy_regs[32]; 67f49856d4SPeter Crosthwaite 68f49856d4SPeter Crosthwaite uint8_t phy_loop; /* Are we in phy loopback? */ 69f49856d4SPeter Crosthwaite 70f49856d4SPeter Crosthwaite /* The current DMA descriptor pointers */ 712bf57f73SAlistair Francis uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES]; 722bf57f73SAlistair Francis uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES]; 73f49856d4SPeter Crosthwaite 74f49856d4SPeter Crosthwaite uint8_t can_rx_state; /* Debug only */ 75f49856d4SPeter Crosthwaite 762bf57f73SAlistair Francis unsigned rx_desc[MAX_PRIORITY_QUEUES][2]; 77f49856d4SPeter Crosthwaite 78f49856d4SPeter Crosthwaite bool sar_active[4]; 79f49856d4SPeter Crosthwaite } CadenceGEMState; 80f49856d4SPeter Crosthwaite 81f49856d4SPeter Crosthwaite #define CADENCE_GEM_H 82f49856d4SPeter Crosthwaite #endif 83