1*211e701dSPeter Maydell /* 2*211e701dSPeter Maydell * ARM TrustZone master security controller emulation 3*211e701dSPeter Maydell * 4*211e701dSPeter Maydell * Copyright (c) 2018 Linaro Limited 5*211e701dSPeter Maydell * Written by Peter Maydell 6*211e701dSPeter Maydell * 7*211e701dSPeter Maydell * This program is free software; you can redistribute it and/or modify 8*211e701dSPeter Maydell * it under the terms of the GNU General Public License version 2 or 9*211e701dSPeter Maydell * (at your option) any later version. 10*211e701dSPeter Maydell */ 11*211e701dSPeter Maydell 12*211e701dSPeter Maydell /* 13*211e701dSPeter Maydell * This is a model of the TrustZone master security controller (MSC). 14*211e701dSPeter Maydell * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM 15*211e701dSPeter Maydell * (DDI 0571G): 16*211e701dSPeter Maydell * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g 17*211e701dSPeter Maydell * 18*211e701dSPeter Maydell * The MSC sits in front of a device which can be a bus master (such as 19*211e701dSPeter Maydell * a DMA controller) and allows secure software to configure it to either 20*211e701dSPeter Maydell * pass through or reject transactions made by that bus master. 21*211e701dSPeter Maydell * Rejected transactions may be configured to either be aborted, or to 22*211e701dSPeter Maydell * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction. 23*211e701dSPeter Maydell * 24*211e701dSPeter Maydell * The MSC has no register interface -- it is configured purely by a 25*211e701dSPeter Maydell * collection of input signals from other hardware in the system. Typically 26*211e701dSPeter Maydell * they are either hardwired or exposed in an ad-hoc register interface by 27*211e701dSPeter Maydell * the SoC that uses the MSC. 28*211e701dSPeter Maydell * 29*211e701dSPeter Maydell * We don't currently implement the irq_enable GPIO input, because on 30*211e701dSPeter Maydell * the MPS2 FPGA images it is always tied high, which is awkward to 31*211e701dSPeter Maydell * implement in QEMU. 32*211e701dSPeter Maydell * 33*211e701dSPeter Maydell * QEMU interface: 34*211e701dSPeter Maydell * + Named GPIO input "cfg_nonsec": set to 1 if the bus master should be 35*211e701dSPeter Maydell * treated as nonsecure, or 0 for secure 36*211e701dSPeter Maydell * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should 37*211e701dSPeter Maydell * result in a transaction error, or 0 for the transaction to RAZ/WI 38*211e701dSPeter Maydell * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt 39*211e701dSPeter Maydell * + Named GPIO output "irq": set for a transaction-failed interrupt 40*211e701dSPeter Maydell * + Property "downstream": MemoryRegion defining where bus master transactions 41*211e701dSPeter Maydell * are made if they are not blocked 42*211e701dSPeter Maydell * + Property "idau": an object implementing IDAUInterface, which defines which 43*211e701dSPeter Maydell * addresses should be treated as secure and which as non-secure. 44*211e701dSPeter Maydell * This need not be the same IDAU as the one used by the CPU. 45*211e701dSPeter Maydell * + sysbus MMIO region 0: MemoryRegion defining the upstream end of the MSC; 46*211e701dSPeter Maydell * this should be passed to the bus master device as the region it should 47*211e701dSPeter Maydell * make memory transactions to 48*211e701dSPeter Maydell */ 49*211e701dSPeter Maydell 50*211e701dSPeter Maydell #ifndef TZ_MSC_H 51*211e701dSPeter Maydell #define TZ_MSC_H 52*211e701dSPeter Maydell 53*211e701dSPeter Maydell #include "hw/sysbus.h" 54*211e701dSPeter Maydell #include "target/arm/idau.h" 55*211e701dSPeter Maydell 56*211e701dSPeter Maydell #define TYPE_TZ_MSC "tz-msc" 57*211e701dSPeter Maydell #define TZ_MSC(obj) OBJECT_CHECK(TZMSC, (obj), TYPE_TZ_MSC) 58*211e701dSPeter Maydell 59*211e701dSPeter Maydell typedef struct TZMSC { 60*211e701dSPeter Maydell /*< private >*/ 61*211e701dSPeter Maydell SysBusDevice parent_obj; 62*211e701dSPeter Maydell 63*211e701dSPeter Maydell /*< public >*/ 64*211e701dSPeter Maydell 65*211e701dSPeter Maydell /* State: these just track the values of our input signals */ 66*211e701dSPeter Maydell bool cfg_nonsec; 67*211e701dSPeter Maydell bool cfg_sec_resp; 68*211e701dSPeter Maydell bool irq_clear; 69*211e701dSPeter Maydell /* State: are we asserting irq ? */ 70*211e701dSPeter Maydell bool irq_status; 71*211e701dSPeter Maydell 72*211e701dSPeter Maydell qemu_irq irq; 73*211e701dSPeter Maydell MemoryRegion *downstream; 74*211e701dSPeter Maydell AddressSpace downstream_as; 75*211e701dSPeter Maydell MemoryRegion upstream; 76*211e701dSPeter Maydell IDAUInterface *idau; 77*211e701dSPeter Maydell } TZMSC; 78*211e701dSPeter Maydell 79*211e701dSPeter Maydell #endif 80