1 /* 2 * STM32L4X5 RCC (Reset and clock control) 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * The reference used is the STMicroElectronics RM0351 Reference manual 13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 14 * 15 * Inspired by the BCM2835 CPRMAN clock manager by Luc Michel. 16 */ 17 18 #ifndef HW_STM32L4X5_RCC_H 19 #define HW_STM32L4X5_RCC_H 20 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 24 #define TYPE_STM32L4X5_RCC "stm32l4x5-rcc" 25 OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5RccState, STM32L4X5_RCC) 26 27 /* In the Stm32l4x5 clock tree, mux have at most 7 sources */ 28 #define RCC_NUM_CLOCK_MUX_SRC 7 29 /* NB: Prescaler are assimilated to mux with one source and one output */ 30 typedef enum RccClockMux { 31 /* Internal muxes that arent't exposed publicly to other peripherals */ 32 RCC_CLOCK_MUX_SYSCLK, 33 RCC_CLOCK_MUX_PLL_INPUT, 34 RCC_CLOCK_MUX_HCLK, 35 RCC_CLOCK_MUX_PCLK1, 36 RCC_CLOCK_MUX_PCLK2, 37 RCC_CLOCK_MUX_HSE_OVER_32, 38 RCC_CLOCK_MUX_LCD_AND_RTC_COMMON, 39 40 /* Muxes with a publicly available output */ 41 RCC_CLOCK_MUX_CORTEX_REFCLK, 42 RCC_CLOCK_MUX_USART1, 43 RCC_CLOCK_MUX_USART2, 44 RCC_CLOCK_MUX_USART3, 45 RCC_CLOCK_MUX_UART4, 46 RCC_CLOCK_MUX_UART5, 47 RCC_CLOCK_MUX_LPUART1, 48 RCC_CLOCK_MUX_I2C1, 49 RCC_CLOCK_MUX_I2C2, 50 RCC_CLOCK_MUX_I2C3, 51 RCC_CLOCK_MUX_LPTIM1, 52 RCC_CLOCK_MUX_LPTIM2, 53 RCC_CLOCK_MUX_SWPMI1, 54 RCC_CLOCK_MUX_MCO, 55 RCC_CLOCK_MUX_LSCO, 56 RCC_CLOCK_MUX_DFSDM1, 57 RCC_CLOCK_MUX_ADC, 58 RCC_CLOCK_MUX_CLK48, 59 RCC_CLOCK_MUX_SAI1, 60 RCC_CLOCK_MUX_SAI2, 61 62 /* 63 * Mux that have only one input and one output assigned to as peripheral. 64 * They could be direct lines but it is simpler 65 * to use the same logic for all outputs. 66 */ 67 /* - AHB1 */ 68 RCC_CLOCK_MUX_TSC, 69 RCC_CLOCK_MUX_CRC, 70 RCC_CLOCK_MUX_FLASH, 71 RCC_CLOCK_MUX_DMA2, 72 RCC_CLOCK_MUX_DMA1, 73 74 /* - AHB2 */ 75 RCC_CLOCK_MUX_RNG, 76 RCC_CLOCK_MUX_AES, 77 RCC_CLOCK_MUX_OTGFS, 78 RCC_CLOCK_MUX_GPIOA, 79 RCC_CLOCK_MUX_GPIOB, 80 RCC_CLOCK_MUX_GPIOC, 81 RCC_CLOCK_MUX_GPIOD, 82 RCC_CLOCK_MUX_GPIOE, 83 RCC_CLOCK_MUX_GPIOF, 84 RCC_CLOCK_MUX_GPIOG, 85 RCC_CLOCK_MUX_GPIOH, 86 87 /* - AHB3 */ 88 RCC_CLOCK_MUX_QSPI, 89 RCC_CLOCK_MUX_FMC, 90 91 /* - APB1 */ 92 RCC_CLOCK_MUX_OPAMP, 93 RCC_CLOCK_MUX_DAC1, 94 RCC_CLOCK_MUX_PWR, 95 RCC_CLOCK_MUX_CAN1, 96 RCC_CLOCK_MUX_SPI3, 97 RCC_CLOCK_MUX_SPI2, 98 RCC_CLOCK_MUX_WWDG, 99 RCC_CLOCK_MUX_LCD, 100 RCC_CLOCK_MUX_TIM7, 101 RCC_CLOCK_MUX_TIM6, 102 RCC_CLOCK_MUX_TIM5, 103 RCC_CLOCK_MUX_TIM4, 104 RCC_CLOCK_MUX_TIM3, 105 RCC_CLOCK_MUX_TIM2, 106 107 /* - APB2 */ 108 RCC_CLOCK_MUX_TIM17, 109 RCC_CLOCK_MUX_TIM16, 110 RCC_CLOCK_MUX_TIM15, 111 RCC_CLOCK_MUX_TIM8, 112 RCC_CLOCK_MUX_SPI1, 113 RCC_CLOCK_MUX_TIM1, 114 RCC_CLOCK_MUX_SDMMC1, 115 RCC_CLOCK_MUX_FW, 116 RCC_CLOCK_MUX_SYSCFG, 117 118 /* - BDCR */ 119 RCC_CLOCK_MUX_RTC, 120 121 /* - OTHER */ 122 RCC_CLOCK_MUX_CORTEX_FCLK, 123 124 RCC_NUM_CLOCK_MUX 125 } RccClockMux; 126 127 typedef struct RccClockMuxState { 128 DeviceState parent_obj; 129 130 RccClockMux id; 131 Clock *srcs[RCC_NUM_CLOCK_MUX_SRC]; 132 Clock *out; 133 bool enabled; 134 uint32_t src; 135 uint32_t multiplier; 136 uint32_t divider; 137 138 /* 139 * Used by clock srcs update callback to retrieve both the clock and the 140 * source number. 141 */ 142 struct RccClockMuxState *backref[RCC_NUM_CLOCK_MUX_SRC]; 143 } RccClockMuxState; 144 145 struct Stm32l4x5RccState { 146 SysBusDevice parent_obj; 147 148 MemoryRegion mmio; 149 150 uint32_t cr; 151 uint32_t icscr; 152 uint32_t cfgr; 153 uint32_t pllcfgr; 154 uint32_t pllsai1cfgr; 155 uint32_t pllsai2cfgr; 156 uint32_t cier; 157 uint32_t cifr; 158 uint32_t ahb1rstr; 159 uint32_t ahb2rstr; 160 uint32_t ahb3rstr; 161 uint32_t apb1rstr1; 162 uint32_t apb1rstr2; 163 uint32_t apb2rstr; 164 uint32_t ahb1enr; 165 uint32_t ahb2enr; 166 uint32_t ahb3enr; 167 uint32_t apb1enr1; 168 uint32_t apb1enr2; 169 uint32_t apb2enr; 170 uint32_t ahb1smenr; 171 uint32_t ahb2smenr; 172 uint32_t ahb3smenr; 173 uint32_t apb1smenr1; 174 uint32_t apb1smenr2; 175 uint32_t apb2smenr; 176 uint32_t ccipr; 177 uint32_t bdcr; 178 uint32_t csr; 179 180 /* Clock sources */ 181 Clock *gnd; 182 Clock *hsi16_rc; 183 Clock *msi_rc; 184 Clock *hse; 185 Clock *lsi_rc; 186 Clock *lse_crystal; 187 Clock *sai1_extclk; 188 Clock *sai2_extclk; 189 190 /* Muxes ~= outputs */ 191 RccClockMuxState clock_muxes[RCC_NUM_CLOCK_MUX]; 192 193 qemu_irq irq; 194 uint64_t hse_frequency; 195 uint64_t sai1_extclk_frequency; 196 uint64_t sai2_extclk_frequency; 197 }; 198 199 #endif /* HW_STM32L4X5_RCC_H */ 200