1*0d952994SBin Meng /* 2*0d952994SBin Meng * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface 3*0d952994SBin Meng * 4*0d952994SBin Meng * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 5*0d952994SBin Meng * 6*0d952994SBin Meng * This program is free software; you can redistribute it and/or modify it 7*0d952994SBin Meng * under the terms and conditions of the GNU General Public License, 8*0d952994SBin Meng * version 2 or later, as published by the Free Software Foundation. 9*0d952994SBin Meng * 10*0d952994SBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 11*0d952994SBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*0d952994SBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*0d952994SBin Meng * more details. 14*0d952994SBin Meng * 15*0d952994SBin Meng * You should have received a copy of the GNU General Public License along with 16*0d952994SBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 17*0d952994SBin Meng */ 18*0d952994SBin Meng 19*0d952994SBin Meng #ifndef HW_SIFIVE_U_PRCI_H 20*0d952994SBin Meng #define HW_SIFIVE_U_PRCI_H 21*0d952994SBin Meng 22*0d952994SBin Meng #define SIFIVE_U_PRCI_HFXOSCCFG 0x00 23*0d952994SBin Meng #define SIFIVE_U_PRCI_COREPLLCFG0 0x04 24*0d952994SBin Meng #define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C 25*0d952994SBin Meng #define SIFIVE_U_PRCI_DDRPLLCFG1 0x10 26*0d952994SBin Meng #define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C 27*0d952994SBin Meng #define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20 28*0d952994SBin Meng #define SIFIVE_U_PRCI_CORECLKSEL 0x24 29*0d952994SBin Meng #define SIFIVE_U_PRCI_DEVICESRESET 0x28 30*0d952994SBin Meng #define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C 31*0d952994SBin Meng 32*0d952994SBin Meng /* 33*0d952994SBin Meng * Current FU540-C000 manual says ready bit is at bit 29, but 34*0d952994SBin Meng * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31. 35*0d952994SBin Meng * We have to trust the actual code that works. 36*0d952994SBin Meng * 37*0d952994SBin Meng * see https://github.com/sifive/freedom-u540-c000-bootloader 38*0d952994SBin Meng */ 39*0d952994SBin Meng 40*0d952994SBin Meng #define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30) 41*0d952994SBin Meng #define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31) 42*0d952994SBin Meng 43*0d952994SBin Meng /* xxxPLLCFG0 register bits */ 44*0d952994SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0) 45*0d952994SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6) 46*0d952994SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15) 47*0d952994SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25) 48*0d952994SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31) 49*0d952994SBin Meng 50*0d952994SBin Meng /* xxxPLLCFG1 register bits */ 51*0d952994SBin Meng #define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24) 52*0d952994SBin Meng 53*0d952994SBin Meng /* coreclksel register bits */ 54*0d952994SBin Meng #define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0) 55*0d952994SBin Meng 56*0d952994SBin Meng 57*0d952994SBin Meng #define SIFIVE_U_PRCI_REG_SIZE 0x1000 58*0d952994SBin Meng 59*0d952994SBin Meng #define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci" 60*0d952994SBin Meng 61*0d952994SBin Meng #define SIFIVE_U_PRCI(obj) \ 62*0d952994SBin Meng OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI) 63*0d952994SBin Meng 64*0d952994SBin Meng typedef struct SiFiveUPRCIState { 65*0d952994SBin Meng /*< private >*/ 66*0d952994SBin Meng SysBusDevice parent_obj; 67*0d952994SBin Meng 68*0d952994SBin Meng /*< public >*/ 69*0d952994SBin Meng MemoryRegion mmio; 70*0d952994SBin Meng uint32_t hfxosccfg; 71*0d952994SBin Meng uint32_t corepllcfg0; 72*0d952994SBin Meng uint32_t ddrpllcfg0; 73*0d952994SBin Meng uint32_t ddrpllcfg1; 74*0d952994SBin Meng uint32_t gemgxlpllcfg0; 75*0d952994SBin Meng uint32_t gemgxlpllcfg1; 76*0d952994SBin Meng uint32_t coreclksel; 77*0d952994SBin Meng uint32_t devicesreset; 78*0d952994SBin Meng uint32_t clkmuxstatus; 79*0d952994SBin Meng } SiFiveUPRCIState; 80*0d952994SBin Meng 81*0d952994SBin Meng #endif /* HW_SIFIVE_U_PRCI_H */ 82